loadpatents
name:-0.0044012069702148
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name:-0.0014870166778564
Tau-Metrix, Inc. Patent Filings

Tau-Metrix, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tau-Metrix, Inc..The latest application filed is for "integrated photodiode for semiconductor substrates".

Company Profile
0.13.3
  • Tau-Metrix, Inc. - Santa Clara CA US
  • tau-Metrix, Inc. - Fremont CA
  • tau-Metrix, Inc. - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated Photodiode For Semiconductor Substrates
App 20160104812 - Steinbrueck; Gary ;   et al.
2016-04-14
Contactless technique for evaluating a fabrication of a wafer
Grant 8,990,759 - Aghababazadeh , et al. March 24, 2
2015-03-24
Integrated photodiode for semiconductor substrates
Grant 8,872,297 - Steinbrueck , et al. October 28, 2
2014-10-28
Integrated Photodiode For Semiconductor Substrates
App 20130334644 - Steinbrueck; Gary ;   et al.
2013-12-19
Integrated photodiode for semiconductor substrates
Grant 8,410,568 - Steinbrueck , et al. April 2, 2
2013-04-02
Test structures for evaluating a fabrication of a die or a wafer
Grant 8,344,745 - Aghababazadeh , et al. January 1, 2
2013-01-01
System and apparatus for using test structures inside of a chip during the fabrication of the chip
Grant 7,736,916 - Aghababazadeh , et al. June 15, 2
2010-06-15
Contactless technique for evaluating a fabrication of a wafer
Grant 7,730,434 - Aghababazadeh , et al. June 1, 2
2010-06-01
System for using test structures to evaluate a fabrication of a wafer
Grant 7,723,724 - Aghababazadeh , et al. May 25, 2
2010-05-25
Intra-chip power and test signal generation for use with test structures on wafers
Grant 7,605,597 - Aghababazadeh , et al. October 20, 2
2009-10-20
Technique for evaluating a fabrication of a die and wafer
Grant 7,423,288 - Aghababazadeh , et al. September 9, 2
2008-09-09
Intra-clip power and test signal generation for use with test structures on wafers
Grant 7,339,388 - Aghababazadeh , et al. March 4, 2
2008-03-04
System and apparatus for using test structures inside of a chip during the fabrication of the chip
Grant 7,256,055 - Aghababazadeh , et al. August 14, 2
2007-08-14
Technique for evaluating a fabrication of a die and wafer
Grant 7,220,990 - Aghababazadeh , et al. May 22, 2
2007-05-22
Company Registrations
SEC0001362978tau Metrix Inc

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