Tate; Naoto

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tate; Naoto.The latest application filed is for "process for treating substrates for the microelectronics industry, and substrates obtained by this process".

Company Profile

0.14.5

Tate; Naoto - Annaka Gunma JP
Tate; Naoto - Annaka JP
Tate; Naoto - Gunma JP
Tate, Naoto - Annaka-shi JP
Tate, Naoto - Gunma-ken JP
Tate; Naoto - Camas WA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Process for treating substrates for the microelectronics industry, and substrates obtained by this process Grant 7,288,418 - Barge , et al. October 30, 2	2007-10-30
Process for treating substrates for the microelectronics industry, and substrates obtained by this process App 20060189102 - Barge; Thierry ; et al.	2006-08-24
Method for treating substrates for microelectronics and substrates obtained according to said method Grant 7,029,993 - Barge , et al. April 18, 2	2006-04-18
Method of manufacturing a bonded wafers using a Bernoulli chuck Grant 6,897,124 - Tate , et al. May 24, 2	2005-05-24
Method for producing SOI wafer and SOI wafer Grant 6,846,718 - Aga , et al. January 25, 2	2005-01-25
Method for manufacturing bonded wafers App 20040152283 - Tate, Naoto ; et al.	2004-08-05
Method for reclaiming delaminated wafer and reclaimed delaminated wafer Grant 6,720,640 - Kuwabara , et al. April 13, 2	2004-04-13
Method for producing SOI wafer and SOI wafer App 20040063298 - Aga, Hiroji ; et al.	2004-04-01
Method for reclaiming delaminated wafer and reclaimed delaminated wafer App 20030219957 - Kuwabara, Susumu ; et al.	2003-11-27
Method for reclaiming delaminated wafer and reclaimed delaminated wafer Grant 6,596,610 - Kuwabara , et al. July 22, 2	2003-07-22
Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method Grant 6,372,609 - Aga , et al. April 16, 2	2002-04-16
Method of fabricating an SOI wafer and SOI wafer fabricated by the method App 20010046746 - Yokokawa, Isao ; et al.	2001-11-29
Method of fabricating an SOI wafer and SOI wafer fabricated by the method Grant 6,284,629 - Yokokawa , et al. September 4, 2	2001-09-04
Method of chemical vapor deposition Grant 6,254,933 - Habuka , et al. July 3, 2	2001-07-03
Silicon and oxygen ion co-implantation for metallic gettering in epitaxial wafers Grant 6,022,793 - Wijaranakula , et al. February 8, 2	2000-02-08
Method for vapor phase growth Grant 5,938,840 - Habuka , et al. August 17, 1	1999-08-17
Back side damage monitoring system Grant 5,764,353 - Tate , et al. June 9, 1	1998-06-09
Method for vapor phase growth Grant 5,755,878 - Habuka , et al. May 26, 1	1998-05-26
Method of chemical vapor deposition and reactor therefor Grant 5,749,974 - Habuka , et al. May 12, 1	1998-05-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.