| Patent | Date |
|---|
Platform and method of operating for integrated end-to-end fully self-aligned interconnect process
Grant 11,456,212 - Clark , et al. September 27, 2 | 2022-09-27 |
Platform and method of operating for integrated end-to-end self-aligned multi-patterning process
Grant 11,398,379 - Clark , et al. July 26, 2 | 2022-07-26 |
Bilayer Dielectric Stack For A Ferroelectric Tunnel Junction And Method Of Forming
App 20220223608 - Consiglio; Steven ; et al. | 2022-07-14 |
Substrate Processing Tool With Integrated Metrology And Method Of Using
App 20220181176 - CLARK; Robert ; et al. | 2022-06-09 |
Self-aligned contacts for 3D logic and memory
Grant 11,335,599 - Liebmann , et al. May 17, 2 | 2022-05-17 |
Method For Threshold Voltage Tuning Through Selective Deposition Of High-k Metal Gate (hkmg) Film Stacks
App 20220148924 - SMITH; Jeffrey ; et al. | 2022-05-12 |
Reverse contact and silicide process for three-dimensional semiconductor devices
Grant 11,322,401 - Smith , et al. May 3, 2 | 2022-05-03 |
Method Of Forming A Semiconductor Device With Air Gaps For Low Capacitance Interconnects
App 20220130723 - Tapily; Kandabara | 2022-04-28 |
Coaxial Contacts For 3d Logic And Memory
App 20220130864 - Liebmann; Lars ; et al. | 2022-04-28 |
Platform and method of operating for integrated end-to-end area-selective deposition process
Grant 11,302,588 - Clark , et al. April 12, 2 | 2022-04-12 |
Architecture Design And Processes For Manufacturing Monolithically Integrated 3d Cmos Logic And Memory
App 20220085012 - Liebmann; Lars ; et al. | 2022-03-17 |
Substrate processing tool with integrated metrology and method of using
Grant 11,264,254 - Tapily , et al. March 1, 2 | 2022-03-01 |
Reverse contact and silicide process for three-dimensional logic devices
Grant 11,264,274 - Smith , et al. March 1, 2 | 2022-03-01 |
Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks
Grant 11,264,289 - Smith , et al. March 1, 2 | 2022-03-01 |
Formation Of Low-temperature And High-temperature In-situ Doped Source And Drain Epitaxy Using Selective Heating For Wrap-around Contact And Vertically Stacked Device Architectures
App 20220051905 - SMITH; Jeffrey ; et al. | 2022-02-17 |
Coaxial contacts for 3D logic and memory
Grant 11,251,200 - Liebmann , et al. February 15, 2 | 2022-02-15 |
Method of forming a semiconductor device with air gaps for low capacitance interconnects
Grant 11,251,077 - Tapily February 15, 2 | 2022-02-15 |
Architecture design of monolithically integrated 3D CMOS logic and memory
Grant 11,217,583 - Liebmann , et al. January 4, 2 | 2022-01-04 |
Power Distribution Network For 3d Logic And Memory
App 20210351132 - Liebmann; Lars ; et al. | 2021-11-11 |
Area selective deposition for cap layer formation in advanced contacts
Grant 11,170,992 - Tapily , et al. November 9, 2 | 2021-11-09 |
Platform and method of operating for integrated end-to-end area-selective deposition process
Grant 11,152,268 - Clark , et al. October 19, 2 | 2021-10-19 |
Method of forming titanium nitride films with (200) crystallographic texture
Grant 11,152,207 - Tapily October 19, 2 | 2021-10-19 |
Method For Filling Recessed Features In Semiconductor Devices With A Low-resistivity Metal
App 20210287936 - Yu; Kai-Hung ; et al. | 2021-09-16 |
Power distribution network for 3D logic and memory
Grant 11,114,381 - Liebmann , et al. September 7, 2 | 2021-09-07 |
Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same
Grant 11,101,173 - Clark , et al. August 24, 2 | 2021-08-24 |
Fully Self-aligned Via With Selective Bilayer Dielectric Regrowth
App 20210249305 - TAPILY; Kandabara ; et al. | 2021-08-12 |
Localized Etch Stop Layer
App 20210242089 - Han; Yun ; et al. | 2021-08-05 |
Method For Controlling The Forming Voltage In Resistive Random Access Memory Devices
App 20210234096 - Consiglio; Steven ; et al. | 2021-07-29 |
Fully self-aligned via with selective bilayer dielectric regrowth
Grant 11,031,287 - Tapily , et al. June 8, 2 | 2021-06-08 |
Method for filling recessed features in semiconductor devices with a low-resistivity metal
Grant 11,024,535 - Yu , et al. June 1, 2 | 2021-06-01 |
Platform And Method Of Operating For Integrated End-to-end Fully Self-aligned Interconnect Process
App 20210125863 - CLARK; Robert ; et al. | 2021-04-29 |
Method for controlling the forming voltage in resistive random access memory devices
Grant 10,991,881 - Consiglio , et al. April 27, 2 | 2021-04-27 |
Reverse Contact And Silicide Process For Three-dimensional Semiconductor Devices
App 20210098294 - SMITH; Jeffrey ; et al. | 2021-04-01 |
Reverse Contact And Silicide Process For Three-dimensional Logic Devices
App 20210098306 - Smith; Jeffrey ; et al. | 2021-04-01 |
Method Of Selective Deposition For Forming Fully Self-aligned Vias
App 20210074584 - Tapily; Kandabara | 2021-03-11 |
Extension region for a semiconductor device
Grant 10,930,764 - Tapily , et al. February 23, 2 | 2021-02-23 |
Platform and method of operating for integrated end-to-end fully self-aligned interconnect process
Grant 10,923,394 - Clark , et al. February 16, 2 | 2021-02-16 |
Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same
Grant 10,916,472 - Clark , et al. February 9, 2 | 2021-02-09 |
Method For Threshold Voltage Tuning Through Selective Deposition Of High-k Metal Gate (hkmg) Film Stacks
App 20210013111 - SMITH; Jeffrey ; et al. | 2021-01-14 |
Platform and method of operating for integrated end-to-end fully self-aligned interconnect process
Grant 10,886,173 - Clark , et al. January 5, 2 | 2021-01-05 |
Method For Controlling The Forming Voltage In Resistive Random Access Memory Devices
App 20200381624 - Consiglio; Steven ; et al. | 2020-12-03 |
Self-aligned Contacts For 3d Logic And Memory
App 20200373203 - Liebmann; Lars ; et al. | 2020-11-26 |
Coaxial Contacts For 3d Logic And Memory
App 20200373330 - Liebmann; Lars ; et al. | 2020-11-26 |
Method for forming a nanowire device
Grant 10,847,424 - Tapily , et al. November 24, 2 | 2020-11-24 |
Method of selective deposition for forming fully self-aligned vias
Grant 10,847,363 - Tapily November 24, 2 | 2020-11-24 |
Integrated In-situ Dry Surface Preparation And Area Selective Film Deposition
App 20200328078 - Tapily; Kandabara | 2020-10-15 |
Three-dimensional device and method of forming the same
Grant 10,770,479 - Smith , et al. Sep | 2020-09-08 |
Method of protecting low-K layers
Grant 10,734,278 - Aizawa , et al. | 2020-08-04 |
Platform and method of operating for integrated end-to-end self-aligned multi-patterning process
Grant 10,727,057 - Clark , et al. | 2020-07-28 |
Method For Filling Recessed Features In Semiconductor Devices With A Low-resistivity Metal
App 20200118871 - Yu; Kai-Hung ; et al. | 2020-04-16 |
Extension Region For A Semiconductor Device
App 20200098897 - Tapily; Kandabara ; et al. | 2020-03-26 |
Self-aware And Correcting Heterogenous Platform Incorporating Integrated Semiconductor Processing Modules And Method For Using S
App 20200081423 - Clark; Robert ; et al. | 2020-03-12 |
Self-aware And Correcting Heterogenous Platform Incorporating Integrated Semiconductor Processing Modules And Method For Using S
App 20200083070 - Clark; Robert ; et al. | 2020-03-12 |
Self-aware And Correcting Heterogenous Platform Incorporating Integrated Semiconductor Processing Modules And Method For Using S
App 20200083080 - Clark; Robert ; et al. | 2020-03-12 |
Self-aware And Correcting Heterogenous Platform Incorporating Integrated Semiconductor Processing Modules And Method For Using S
App 20200083074 - Clark; Robert ; et al. | 2020-03-12 |
Buried power rails
Grant 10,586,765 - Smith , et al. | 2020-03-10 |
Method of selective film deposition for forming fully self-aligned vias
Grant 10,586,734 - Tapily | 2020-03-10 |
Architecture Design And Processes For Manufacturing Monolithically Integrated 3d Cmos Logic And Memory
App 20200075592 - Liebmann; Lars ; et al. | 2020-03-05 |
Method To Vertically Route A Logic Cell Incorporating Stacked Transistors In A Three Dimensional Logic Device
App 20200075574 - SMITH; Jeffrey ; et al. | 2020-03-05 |
Power Distribution Network For 3d Logic And Memory
App 20200075489 - Liebmann; Lars ; et al. | 2020-03-05 |
Method Of Forming Titanium Nitride Films With (200) Crystallographic Texture
App 20200035481 - Tapily; Kandabara | 2020-01-30 |
Extension region for a semiconductor device
Grant 10,529,830 - Tapily , et al. J | 2020-01-07 |
Fully Self-aligned Via With Selective Bilayer Dielectric Regrowth
App 20200006140 - TAPILY; Kandabara ; et al. | 2020-01-02 |
Method For Forming A Nanowire Device
App 20190393097 - Tapily; Kandabara ; et al. | 2019-12-26 |
Method of Protecting Low-K Layers
App 20190385906 - Aizawa; Hirokazu ; et al. | 2019-12-19 |
Area Selective Deposition For Cap Layer Formation In Advanced Contacts
App 20190333763 - Tapily; Kandabara ; et al. | 2019-10-31 |
Removal method and processing method
Grant 10,460,988 - Itatani , et al. Oc | 2019-10-29 |
Method Of Forming A Semiconductor Device With Air Gaps For Low Capacitance Interconnects
App 20190311947 - Tapily; Kandabara ; et al. | 2019-10-10 |
Platform And Method Of Operating For Integrated End-to-end Area-selective Deposition Process
App 20190295845 - Clark; Robert ; et al. | 2019-09-26 |
Platform And Method Of Operating For Integrated End-to-end Fully Self-aligned Interconnect Process
App 20190295891 - Clark; Robert ; et al. | 2019-09-26 |
Platform And Method Of Operating For Integrated End-to-end Area-selective Deposition Process
App 20190295903 - Clark; Robert ; et al. | 2019-09-26 |
Platform And Method Of Operating For Integrated End-to-end Self-aligned Multi-patterning Process
App 20190295906 - Clark; Robert ; et al. | 2019-09-26 |
Platform And Method Of Operating For Integrated End-to-end Fully Self-aligned Interconnect Process
App 20190295890 - Clark; Robert ; et al. | 2019-09-26 |
Substrate Processing Tool With Integrated Metrology And Method Of Using
App 20190295870 - Tapily; Kandabara ; et al. | 2019-09-26 |
Platform And Method Of Operating For Integrated End-to-end Self-aligned Multi-patterning Process
App 20190295846 - Clark; Robert ; et al. | 2019-09-26 |
Three-dimensional Device And Method Of Forming The Same
App 20190288004 - SMITH; Jeffrey ; et al. | 2019-09-19 |
Removal Method And Processing Method
App 20190198390 - ITATANI; Takeshi ; et al. | 2019-06-27 |
Method Of Selective Deposition For Forming Fully Self-aligned Vias
App 20190164749 - Tapily; Kandabara | 2019-05-30 |
Method Of Selective Film Deposition For Forming Fully Self-aligned Vias
App 20190157149 - Tapily; Kandabara | 2019-05-23 |
Buried Power Rails
App 20180374791 - SMITH; Jeffrey ; et al. | 2018-12-27 |
Three-dimensional semiconductor device and method of fabrication
Grant 9,997,598 - Smith , et al. June 12, 2 | 2018-06-12 |
Extension Region For A Semiconductor Device
App 20180047832 - TAPILY; Kandabara ; et al. | 2018-02-15 |
Three-dimensional Semiconductor Device And Method Of Fabrication
App 20180040695 - Smith; Jeffrey ; et al. | 2018-02-08 |
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