Taniguchi; Nobutaka

Patent Applications and Registrations

Patent applications and USPTO patent grants for Taniguchi; Nobutaka.The latest application filed is for "semiconductor device including a clock adjustment circuit".

Company Profile

0.11.11

Taniguchi; Nobutaka - Tokyo JP
Taniguchi; Nobutaka - Kawasaki JP
Taniguchi; Nobutaka - Kanagawa JP
Taniguchi, Nobutaka - Kawasaki-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device including a clock adjustment circuit Grant 9,325,330 - Taniguchi April 26, 2	2016-04-26
Semiconductor Device Including A Clock Adjustment Circuit App 20150097604 - TANIGUCHI; NOBUTAKA	2015-04-09
Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero Grant 7,667,509 - Taniguchi February 23, 2	2010-02-23
Address/data multiplexed device Grant 7,643,371 - Kurihara , et al. January 5, 2	2010-01-05
Address/data Multiplexed Device App 20080159011 - Kurihara; Kazuhiro ; et al.	2008-07-03
Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit Grant 7,307,885 - Ikeda , et al. December 11, 2	2007-12-11
Memory device Grant 7,184,296 - Hatakeyama , et al. February 27, 2	2007-02-27
Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero Grant 7,106,114 - Taniguchi September 12, 2	2006-09-12
Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero App 20060176092 - Taniguchi; Nobutaka	2006-08-10
Memory device App 20050185465 - Taniguchi, Nobutaka ; et al.	2005-08-25
Nonvolatile semiconductor memory device App 20050162955 - Ikeda, Toshimi ; et al.	2005-07-28
Memory device App 20050141306 - Hatakeyama, Atsushi ; et al.	2005-06-30
Integrated circuit device incorporating DLL circuit Grant 6,522,182 - Tomita , et al. February 18, 2	2003-02-18
Semiconductor device with dummy interface circuit App 20020050847 - Taniguchi, Nobutaka ; et al.	2002-05-02
Integrated Circuit Device Incorporating Dll Circuit App 20010043100 - TOMITA, HIROYOSHI ; et al.	2001-11-22
Method for adjusting phase of controlling clock signal and semiconductor integrated circuit having delay locked loop circuit App 20010028266 - Taniguchi, Nobutaka	2001-10-11
Delay time adjusting circuit comprising frequency dividers having different frequency division rates App 20010016022 - Taniguchi, Nobutaka ; et al.	2001-08-23
Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero App 20010015664 - Taniguchi, Nobutaka	2001-08-23
Timing clock generation circuit using hierarchical DLL circuit Grant 6,242,954 - Taniguchi , et al. June 5, 2	2001-06-05
Integrated circuit device Grant 6,194,932 - Takemae , et al. February 27, 2	2001-02-27
Semiconductor integrated circuit device Grant 6,181,174 - Fujieda , et al. January 30, 2	2001-01-30
Semiconductor memory device Grant 5,901,101 - Suzuki , et al. May 4, 1	1999-05-04

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