Tang; Cheng-Long

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tang; Cheng-Long.The latest application filed is for "microprocessor architecture capable of supporting multiple heterogeneous processors".

Company Profile

0.9.3

Tang; Cheng-Long - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 7,657,712 - Lentz , et al. February 2, 2	2010-02-02
Microprocessor architecture capable of supporting multiple heterogeneous processors App 20060064569 - Lentz; Derek J. ; et al.	2006-03-23
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 6,954,844 - Lentz , et al. October 11, 2	2005-10-11
Microprocessor architecture capable of supporting multiple heterogeneous processors App 20040024987 - Lentz, Derek J. ; et al.	2004-02-05
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 6,611,908 - Lentz , et al. August 26, 2	2003-08-26
Microprocessor architecture capable of supporting multiple heterogeneous processors App 20020059508 - Lentz, Derek J. ; et al.	2002-05-16
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 6,272,579 - Lentz , et al. August 7, 2	2001-08-07
System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit Grant 6,219,763 - Lentz , et al. April 17, 2	2001-04-17
System and method for supporting a multiple width memory subsystem Grant 6,047,348 - Lentz , et al. April 4, 2	2000-04-04
Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption Grant 5,754,800 - Lentz , et al. May 19, 1	1998-05-19
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU Grant 5,604,865 - Lentz , et al. February 18, 1	1997-02-18
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU Grant 5,440,752 - Lentz , et al. August 8, 1	1995-08-08

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