Tanaka; Genichi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tanaka; Genichi.The latest application filed is for "circuit simulation method and circuit simulation device".

Company Profile

0.15.17

Tanaka; Genichi - Kanagawa N/A JP
Tanaka; Genichi - Hyogo JP
Tanaka; Genichi - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit simulation method and circuit simulation device Grant 8,718,999 - Tanaka May 6, 2	2014-05-06
Circuit Simulation Method And Circuit Simulation Device App 20110307234 - TANAKA; Genichi	2011-12-15
Scan path timing optimizing apparatus determining connection order of scan path circuits to realize optimum signal timings Grant 7,162,707 - Kanaoka , et al. January 9, 2	2007-01-09
Device for creating timing constraints Grant 7,127,693 - Tanaka October 24, 2	2006-10-24
Automatic placement and routing apparatus for designing integrated circuit that controls its timing using multiple power supplies Grant 7,007,257 - Tanaka February 28, 2	2006-02-28
Method of determining arrangement of wire in semiconductor intergrated circuit App 20040216067 - Tanaka, Genichi ; et al.	2004-10-28
Timing information generating apparatus App 20040210689 - Tanaka, Genichi	2004-10-21
Device for creating timing constraints App 20040194044 - Tanaka, Genichi	2004-09-30
Parasitic element extraction apparatus Grant 6,772,404 - Tanaka August 3, 2	2004-08-03
Automatic placement and routing apparatus Grant 6,763,510 - Tanaka July 13, 2	2004-07-13
Semiconductor integrated circuit Grant 6,759,698 - Tanaka July 6, 2	2004-07-06
Scan path timing optimizing apparatus determining connection order of scan path circuits to realize optimum signal timings App 20040111689 - Kanaoka, Toshihiro ; et al.	2004-06-10
Parasitic Element Extraction Apparatus App 20040103384 - Tanaka, Genichi	2004-05-27
Semiconductor process parameter determining method, semiconductor process parameter determining system, and semiconductor process parameter determining program Grant 6,698,000 - Tanaka February 24, 2	2004-02-24
Automatic placement and routing apparatus for designing integrated circuit that controls its timing using multiple power supplies App 20030221175 - Tanaka, Genichi	2003-11-27
Semiconductor integrated circuit App 20030136977 - Tanaka, Genichi	2003-07-24
Engineering-change method of semiconductor circuit Grant 6,581,199 - Tanaka June 17, 2	2003-06-17
Method and apparatus for extracting parasitic element of semiconductor circuit Grant 6,581,195 - Tanaka June 17, 2	2003-06-17
Automatic placement and routing apparatus App 20030046650 - Tanaka, Genichi	2003-03-06
Automatic cell placement and routing method and semiconductor integrated circuit Grant 6,505,335 - Tanaka January 7, 2	2003-01-07
Automatic placement and routing device and method of automatic placement and routing Grant 6,480,997 - Tanaka November 12, 2	2002-11-12
Image displaying method App 20020154148 - Inoue, Aiichi ; et al.	2002-10-24
Semiconductor process parameter determining method, semiconductor process parameter determining system, and semiconductor process parameter determining program App 20020152059 - Tanaka, Genichi	2002-10-17
Shield circuit and integrated circuit in which the shield circuit is used Grant 6,456,117 - Tanaka September 24, 2	2002-09-24
Engineering-change method of semiconductor circuit App 20020129325 - Tanaka, Genichi	2002-09-12
Method of executing benchmark test App 20020116152 - Tanaka, Genichi	2002-08-22
Shield circuit designing apparatus and shield circuit designing method App 20020074671 - Tanaka, Genichi	2002-06-20
Method and apparatus for extracting parasitic element of semiconductor circuit App 20020056070 - Tanaka, Genichi	2002-05-09
Method and apparatus for designing semiconductor integrated circuits App 20020035719 - Tanaka, Genichi	2002-03-21
Shield circuit and integrated circuit in which the shield circuit is used App 20020008546 - Tanaka, Genichi	2002-01-24
Automatic placement and routing device Grant 6,253,364 - Tanaka , et al. June 26, 2	2001-06-26

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.