Tan; Tat Hin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tan; Tat Hin.The latest application filed is for "generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device".

Company Profile

10.15.12

Tan; Tat Hin - Penang MY
TAN; Tat Hin - Bayan Lepas Pulau Pinang MY
TAN; Tat Hin - Batu Uban MY
Tan; Tat Hin - Bayan Lepas MY
Tan; Tat Hin - Malaysia MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked through-silicon vias for multi-device packages Grant 11,398,415 - Cheah , et al. July 26, 2	2022-07-26
Micro through-silicon via for transistor density scaling Grant 11,393,741 - Cheah , et al. July 19, 2	2022-07-19
Generic Physical Layer Providing A Unified Architecture For Interfacing With An External Memory Device And Methods Of Interfacing With An External Memory Device App 20220208240 - LIM; Soon Chieh ; et al.	2022-06-30
Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device Grant 11,373,694 - Lim , et al. June 28, 2	2022-06-28
Clocking System And A Method Of Clock Synchronization App 20220200610 - TEH; CHEE HAK ; et al.	2022-06-23
Micro Through-silicon Via For Transistor Density Scaling App 20220157694 - CHEAH; Bok Eng ; et al.	2022-05-19
Micro Through-silicon Via For Transistor Density Scaling App 20210320051 - Cheah; Bok Eng ; et al.	2021-10-14
Micro through-silicon via for transistor density scaling Grant 10,903,142 - Cheah , et al. January 26, 2	2021-01-26
Methods for mitigating transistor aging to improve timing margins for memory interface signals Grant 10,714,163 - Tan , et al.	2020-07-14
Stacked Through-silicon Vias For Multi-device Packages App 20200091040 - Cheah; Bok Eng ; et al.	2020-03-19
Micro Through-silicon Via For Transistor Density Scaling App 20200043831 - Cheah; Bok Eng ; et al.	2020-02-06
Methods For Mitigating Transistor Aging To Improve Timing Margins For Memory Interface Signals App 20190267062 - Tan; Tat Hin ; et al.	2019-08-29
High speed sense amplifier latch with low power rail-to-rail input common mode range Grant 10,333,689 - Dudulwar , et al.	2019-06-25
Methods for determining resistive-capacitive component design targets for radio-frequency circuitry Grant 10,223,483 - Tan , et al.	2019-03-05
Dual signal protocol input/output (I/O) buffer circuit Grant 10,224,911 - Tan , et al.	2019-03-05
Systems and methods for extraction of electrical specifications from prelayout simulations Grant 10,198,545 - Tan , et al. Fe	2019-02-05
High resolution and low power interpolator for delay chain Grant 10,200,046 - Leong , et al. Fe	2019-02-05
Integrated circuit with an increased signal bandwidth input/output (I/O) circuit Grant 10,110,225 - Lau , et al. October 23, 2	2018-10-23
Techniques for enabling and disabling transistor legs in an output driver circuit Grant 9,793,888 - Tan , et al. October 17, 2	2017-10-17
Techniques For Enabling And Disabling Transistor Legs In An Output Driver Circuit App 20170264283 - Tan; Tat Hin ; et al.	2017-09-14
High Speed Sense Amplifier Latch With Low Power Rail-to-rail Input Common Mode Range App 20160380753 - Dudulwar; Pankaj Vinayak ; et al.	2016-12-29
High speed sense amplifier latch with low power rail-to-rail input common mode range Grant 9,443,567 - Dudulwar , et al. September 13, 2	2016-09-13
Error correction coding in flash memory devices Grant 8,239,732 - Tan , et al. August 7, 2	2012-08-07
Error Correction Coding In Flash Memory Devices App 20090113272 - Tan; Tat Hin ; et al.	2009-04-30
Offset-compensated self-biased differential amplifier Grant 6,967,532 - Tan November 22, 2	2005-11-22
Offset-compensated self-biased differential amplifier App 20050140442 - Tan, Tat Hin	2005-06-30

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