| Patent | Date |
|---|
Presentation of direct accessed storage under a logical drive model
Grant 11,449,446 - Slaight , et al. September 20, 2 | 2022-09-20 |
Presentation Of Direct Accessed Storage Under A Logical Drive Model
App 20200349100 - Slaight; Thomas M. ; et al. | 2020-11-05 |
Enhanced cyclical redundancy check circuit based on galois-field arithmetic
Grant 9,935,653 - Radhakrishnan , et al. April 3, 2 | 2018-04-03 |
Enhanced Cyclical Redundancy Check Circuit Based On Galois-field Arithmetic
App 20170187389 - Radhakrishnan; Sivakumar ; et al. | 2017-06-29 |
Presentation Of Direct Accessed Storage Under A Logical Drive Model
App 20160335208 - Slaight; Thomas M. ; et al. | 2016-11-17 |
Presentation of direct accessed storage under a logical drive model
Grant 9,417,821 - Slaight , et al. August 16, 2 | 2016-08-16 |
Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
Grant 9,141,469 - Radhakrishnan , et al. September 22, 2 | 2015-09-22 |
Integration of processor and input/output hub
Grant 8,850,250 - Looi , et al. September 30, 2 | 2014-09-30 |
Limiting false wakeups of computing device components coupled via links
Grant 8,812,878 - Tan , et al. August 19, 2 | 2014-08-19 |
Dynamic and idle power reduction sequence using recombinant clock and power gating
Grant 8,782,456 - Tan , et al. July 15, 2 | 2014-07-15 |
Presentation Of Direct Accessed Storage Under A Logical Drive Model
App 20140189212 - Slaight; Thomas M. ; et al. | 2014-07-03 |
Efficient And Scalable Cyclic Redundancy Check Circuit Using Galois-field Arithmetic
App 20140082451 - Radhakrishnan; Sivakumar ; et al. | 2014-03-20 |
Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
Grant 8,607,129 - Radhakrishnan , et al. December 10, 2 | 2013-12-10 |
Efficient And Scalable Cyclic Redundancy Check Circuit Using Galois-field Arithmetic
App 20130007573 - Radhakrishnan; Sivakumar ; et al. | 2013-01-03 |
Power measurement techniques of a system-on-chip (SOC)
Grant 8,275,560 - Radhakrishnan , et al. September 25, 2 | 2012-09-25 |
Integration Of Processor And Input/output Hub
App 20110296216 - Looi; Lily Pao ; et al. | 2011-12-01 |
Dynamic And Idle Power Reduction Sequence Using Recombinant Clock And Power Gating
App 20110296222 - Tan; Sin S. ; et al. | 2011-12-01 |
Power Measurement Techniques Of A System-on-chip (soc)
App 20110060931 - RADHAKRISHNAN; SIVAKUMAR ; et al. | 2011-03-10 |
Squelch Filtration To Limit False Wakeups
App 20100332868 - Tan; Sin S. ; et al. | 2010-12-30 |
Maximal length packets
Grant 7,500,029 - Radhakrishnan , et al. March 3, 2 | 2009-03-03 |
Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions
Grant 7,386,643 - Tan , et al. June 10, 2 | 2008-06-10 |
Maximal length packets
App 20060168384 - Radhakrishnan; Sivakumar ; et al. | 2006-07-27 |
Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions
App 20050060502 - Tan, Sin S. ; et al. | 2005-03-17 |
Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions
Grant 6,832,268 - Tan , et al. December 14, 2 | 2004-12-14 |
Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions
App 20040122995 - Tan, Sin S. ; et al. | 2004-06-24 |
Mechanism for handling conflicts in a multi-node computer architecture
Grant 6,622,215 - Khare , et al. September 16, 2 | 2003-09-16 |
Mechanism for handling conflicts in a multi-node computer architecture
App 20020129206 - Khare, Manoj ; et al. | 2002-09-12 |
Method and apparatus to implement a locked-bus transaction
App 20020087766 - Kumar, Akhilesh ; et al. | 2002-07-04 |
| 