Tam; Clarence K. L.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tam; Clarence K. L..The latest application filed is for "high-speed transceiver tester incorporating jitter injection".
- Tam; Clarence K. L. - Saint-Laurent CA
- Tam; Clarence K. L. - Montreal CA
| Patent | Date |
|---|---|
| Method and apparatus for digital post-distortion compensation of signal non-linearities Grant 8,948,325 - Warner , et al. February 3, 2 | 2015-02-03 |
| High-speed transceiver tester incorporating jitter injection Grant 8,327,204 - Hafed , et al. December 4, 2 | 2012-12-04 |
| System and method for testing integrated circuits Grant 7,242,209 - Roberts , et al. July 10, 2 | 2007-07-10 |
| High-Speed Transceiver Tester Incorporating Jitter Injection App 20070113119 - Hafed; Mohamed M. ; et al. | 2007-05-17 |
| System and method for testing integrated circuits App 20050253617 - Roberts, Gordon W. ; et al. | 2005-11-17 |
| Method and device for use in DC parametric tests Grant 6,917,320 - Roberts , et al. July 12, 2 | 2005-07-12 |
| Method and device for use in DC parametric tests App 20040246002 - Roberts, Gordon W. ; et al. | 2004-12-09 |
| Method and device for use in DC parametric tests Grant 6,727,834 - Roberts , et al. April 27, 2 | 2004-04-27 |
| Method and device for use in DC parametric tests App 20030206127 - Roberts, Gordon W. ; et al. | 2003-11-06 |
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