Talreja; Sanjay S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Talreja; Sanjay S..The latest application filed is for "power saving in nand flash memory".

Company Profile

0.17.4

Talreja; Sanjay S. - Folsom CA US
Talreja; Sanjay S - Folsom CA
Talreja; Sanjay S. - Citrus Heights CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Power saving in NAND flash memory Grant 8,489,780 - Sundaram , et al. July 16, 2	2013-07-16
Power saving in NAND flash memory App 20080155287 - Sundaram; Rajesh ; et al.	2008-06-26
Status register architecture for flexible read-while-write device Grant 6,931,498 - Talreja , et al. August 16, 2	2005-08-16
Method and system to retrieve information Grant 6,920,539 - Qawami , et al. July 19, 2	2005-07-19
Method and system to retrieve information App 20040003192 - Qawami, Shekoufeh ; et al.	2004-01-01
Burst suspend and resume with computer memory Grant 6,618,790 - Talreja , et al. September 9, 2	2003-09-09
Multilevel cell memory architecture App 20030031050 - Talreja, Sanjay S.	2003-02-13
Status register architecture for flexible read-while-write device App 20020144066 - Talreja, Sanjay S. ; et al.	2002-10-03
Method and apparatus for preventing the fraudulent use of a cellular telephone Grant 6,223,290 - Larsen , et al. April 24, 2	2001-04-24
Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks Grant 6,154,819 - Larsen , et al. November 28, 2	2000-11-28
Dynamic single bit per cell to multiple bit per cell memory Grant 6,097,637 - Bauer , et al. August 1, 2	2000-08-01
Controlling flash memory program and erase pulses Grant 5,944,837 - Talreja , et al. August 31, 1	1999-08-31
Controlling flash memory program and erase pulses Grant 5,907,700 - Talreja , et al. May 25, 1	1999-05-25
Hardware reset of a write state machine for flash memory Grant 5,742,787 - Talreja April 21, 1	1998-04-21
Write verify schemes for flash memory with multilevel cells Grant 5,539,690 - Talreja , et al. July 23, 1	1996-07-23
Drain bias multiplexing for multiple bit flash cell Grant 5,485,422 - Bauer , et al. January 16, 1	1996-01-16
User selectable word/byte input architecture for flash EEPROM memory write and erase operations Grant 5,379,413 - Hazen , et al. January 3, 1	1995-01-03
Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays Grant 5,317,535 - Talreja , et al. May 31, 1	1994-05-31
Floating gate nonvolatile memory with configurable erasure blocks Grant 5,280,447 - Hazen , et al. January 18, 1	1994-01-18
Floating gate nonvolatile memory with distributed blocking feature Grant 5,267,196 - Talreja , et al. November 30, 1	1993-11-30

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