loadpatents
name:-0.0034189224243164
name:-0.010857820510864
name:-0.001751184463501
Talledo; Cesar A. Patent Filings

Talledo; Cesar A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Talledo; Cesar A..The latest application filed is for "integrated circuit systems and devices having high precision digital delay lines therein".

Company Profile
0.10.2
  • Talledo; Cesar A. - San Jose CA US
  • Talledo; Cesar A. - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
PCI express switch and method for multi-port non-transparent switching
Grant 8,429,325 - Onufryk , et al. April 23, 2
2013-04-23
Integrated circuit systems and devices having high precision digital delay lines therein
Grant 7,203,126 - Proebsting , et al. April 10, 2
2007-04-10
Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments
Grant 7,061,294 - Talledo , et al. June 13, 2
2006-06-13
Transaction aligner microarchitecture
Grant 7,016,987 - Hussain , et al. March 21, 2
2006-03-21
Integrated circuit systems and devices having high precision digital delay lines therein
App 20050206426 - Proebsting, Robert J. ;   et al.
2005-09-22
Integrated circuit devices having high precision digital delay lines therein
Grant 6,944,070 - Proebsting , et al. September 13, 2
2005-09-13
Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments
Grant 6,867,630 - Talledo , et al. March 15, 2
2005-03-15
Integrated circuit devices having high precision digital delay lines therein
Grant 6,856,558 - Proebsting , et al. February 15, 2
2005-02-15
Apparatus and method for generating a compensated percent-of-clock period delay signal
Grant 6,664,838 - Talledo December 16, 2
2003-12-16
Fly-by support module for a peripheral bus
Grant 6,662,258 - Lukanc , et al. December 9, 2
2003-12-09
Transaction aligner microarchitecture
App 20030018837 - Hussain, Agha B. ;   et al.
2003-01-23

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