loadpatents
Patent applications and USPTO patent grants for Talbot; Gerald.The latest application filed is for "ddr 2d vref training".
Patent | Date |
---|---|
DDR 2D Vref training Grant 9,214,199 - Brandl , et al. December 15, 2 | 2015-12-15 |
DDR receiver enable cycle training Grant 9,183,125 - Brandl , et al. November 10, 2 | 2015-11-10 |
Ddr 2d Vref Training App 20150078104 - Brandl; Kevin M. ;   et al. | 2015-03-19 |
DDR 2D Vref training Grant 8,850,155 - Brandl , et al. September 30, 2 | 2014-09-30 |
Ddr 2d Vref Training App 20130155788 - Brandl; Kevin M. ;   et al. | 2013-06-20 |
Ddr Receiver Enable Cycle Training App 20130159615 - Brandl; Kevin M. ;   et al. | 2013-06-20 |
Microprocessor module with integrated voltage regulators Grant 6,865,682 - Talbot , et al. March 8, 2 | 2005-03-08 |
Dynamic initialization of processor module via motherboard interface Grant 6,772,328 - Talbot , et al. August 3, 2 | 2004-08-03 |
Common motherboard interface for processor modules of multiple architectures Grant 6,516,373 - Talbot , et al. February 4, 2 | 2003-02-04 |
Low voltage differential receiver/transmitter and calibration method thereof Grant 6,448,815 - Talbot , et al. September 10, 2 | 2002-09-10 |
Voltage-controlled oscillator with ac coupling to produce highly accurate duty cycle square wave output App 20020075087 - Talbot, Gerald | 2002-06-20 |
Apparatus and method for mounting a processor circuit board on a system mother board Grant 6,084,774 - Talbot , et al. July 4, 2 | 2000-07-04 |
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