TAKANO; Chiaki

Patent Applications and Registrations

Patent applications and USPTO patent grants for TAKANO; Chiaki.The latest application filed is for "composition".

Company Profile

0.9.9

TAKANO; Chiaki - Shibukawa-city JP
Takano; Chiaki - Austin TX
Takano; Chiaki - Kanagawa JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Composition App 20200231726 - HAYASHI; Hideki ; et al.	2020-07-23
Methods and apparatus for managing clock skew between clock domain boundaries Grant 7,761,748 - Takano July 20, 2	2010-07-20
Method and apparatus for adaptive clock phase control for LSI power reduction Grant 7,733,150 - Takano June 8, 2	2010-06-08
Method and system for rebooting a processor in a multi-processor system Grant 7,676,683 - Tsuji , et al. March 9, 2	2010-03-09
Method And Apparatus For Adaptive Clock Phase Control For Lsi Power Reduction App 20100039152 - Takano; Chiaki	2010-02-18
Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning Grant 7,616,043 - Takano November 10, 2	2009-11-10
Methods and Apparatus For Managing LSI Power Consumption and Degradation Using Clock Signal Conditioning App 20090201055 - Takano; Chiaki	2009-08-13
Method And Apparatus For Scan Chain Circuit AC Test App 20080133989 - Hayashi; Atsushi ; et al.	2008-06-05
Methods and apparatus for reducing duty cycle distortion in a multiple-stage inverter App 20080061829 - Takano; Chiaki	2008-03-13
Method and system for rebooting a processor in a multi-processor system App 20080052504 - Tsuji; Atsushi ; et al.	2008-02-28
Methods and apparatus for managing clock skew Grant 7,301,385 - Takano , et al. November 27, 2	2007-11-27
Methods And Apparatus For Reducing Power Consumption In A Processor Using Clock Signal Control App 20070146037 - Takano; Chiaki ; et al.	2007-06-28
Methods and apparatus for reducing power consumption in a processor using clock signal control Grant 7,233,188 - Takano , et al. June 19, 2	2007-06-19
Methods and apparatus for managing clock skew App 20070063756 - Takano; Chiaki ; et al.	2007-03-22
Methods and apparatus for managing clock skew between clock domain boundaries App 20070011531 - Takano; Chiaki	2007-01-11
Super buffer and DCFL circuits with Schottky barrier diode Grant 5,374,862 - Takano December 20, 1	1994-12-20
Three-dimensional optical-electronic integrated circuit device with raised sections Grant 5,357,122 - Okubora , et al. October 18, 1	1994-10-18
Semiconductor integrated circuit having clock signal generator Grant 5,329,254 - Takano July 12, 1	1994-07-12

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