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Interconnect Features With Sharp Corners and Method Forming Same
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Novel Electrostatic Discharge Protection Circuit
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Gate Contact And Via Structures In Semiconductor Devices
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Reducing K Values of Dielectric Films Through Anneal
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Optimized Layout Cell
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Light source, EUV lithography system, and method for generating EUV radiation
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Memory circuit, electronic device having the memory circuit, and method of operating memory circuit
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Redistribution Lines Having Nano Columns and Method Forming Same
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Semiconductor Device and Method
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Semiconductor Package System and Method
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Photoresist and Method of Formation and Use
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Finfet Devices And Methods Of Forming
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Contact Conductive Feature Formation and Structure
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Soic Chip Architecture
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Systems and methods for wafer pod calibration
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Hard mask removal method
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Semiconductive structure and manufacturing method thereof
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Method and system for diagnosing a semiconductor wafer
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Leakage reduction methods and structures thereof
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Non-volatile memory of semiconductor device and method for manufacturing the same
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Input/output (I/O) devices with greater source/drain proximity than non-I/O devices
Grant 10,074,668 - Ching , et al. September 11, 2 | 2018-09-11 |
Electric magnetic shielding structure in packages
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High Performance Power Cell For Rf Power Amplifier
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Package structure and methods of forming same
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System And Method For Inductive Wireless Signaling
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Grid refinement method
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System And Method For Pattern Correction In E-beam Lithography
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Measuring electrical resistance
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Non-planar Sige Channel Pfet
App 20150137268 - FUNG; KA-HING | 2015-05-21 |
Dual layer microelectromechanical systems device and method of manufacturing same
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Resistive memory cell array with top electrode bit line
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Systems and methods for determining effective capacitance to facilitate a timing analysis
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Backside illumination image sensor chips and methods for forming the same
Grant 8,884,390 - Cheng , et al. November 11, 2 | 2014-11-11 |
Integrated write mux and driver systems and methods
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E-Beam Lithography with Alignment Gating
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Universal design layout compliance
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Method For Inducing Strain In Finfet Channels
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Electronic device and method of manufacturing an electronic device
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Apparatus for ESD protection
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SRAM cell comprising FinFETs
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Packaged semiconductor devices and packaging devices and methods
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HfO.sub.2/SiO.sub.2-Si interface improvement for CMOS image sensor
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Epitaxial process for forming semiconductor devices
Grant 8,598,661 - Wang December 3, 2 | 2013-12-03 |
Cascaded-based de-embedding methodology
Grant 8,436,626 - Cho May 7, 2 | 2013-05-07 |
Device with Engineered Epitaxial Region and Methods of Making Same
App 20130062670 - Wong; King-Yuen ; et al. | 2013-03-14 |
Light-emitting diodes on concave texture substrate
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Metal-Ceramic Multilayer Structure
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Capacitors with insulating layer having embedded dielectric rods
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Introducing a metal layer between SiN and TiN to improve CBD contact resistance for P-TSV
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Self-aligned double gate device and method for forming same
Grant 7,230,270 - Chen , et al. June 12, 2 | 2007-06-12 |
Method and apparatus for fabricating metal layer
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Silicon oxycarbide and silicon carbonitride based materials for MOS devices
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Photomask Esd Protection And An Anti-esd Pod With Such Protection
App 20030013258 - Lee, Fu-Sheng | 2003-01-16 |
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