Tai; Roger

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tai; Roger.The latest application filed is for "interfacial layer between fin and source/drain region".

Company Profile

9.6.8

Tai; Roger - Tainan TW
Tai; Roger - Tainan City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
V-shape recess profile for embedded source/drain epitaxy Grant 11,121,255 - Li , et al. September 14, 2	2021-09-14
Interfacial Layer Between Fin and Source/Drain Region App 20210193831 - Chin; Chih-Yun ; et al.	2021-06-24
Interfacial layer between fin and source/drain region Grant 10,944,005 - Chin , et al. March 9, 2	2021-03-09
V-shape recess profile for embedded source/drain epitaxy Grant 10,763,366 - Li , et al. Sep	2020-09-01
V-Shape Recess Profile for Embedded Source/Drain Epitaxy App 20200273993 - Li; Chii-Horng ; et al.	2020-08-27
V-shape recess profile for embedded source/drain epitaxy Grant 10,651,309 - Li , et al.	2020-05-12
V-Shape Recess Profile for Embedded Source/Drain Epitaxy App 20200052121 - Li; Chii-Horng ; et al.	2020-02-13
Interfacial Layer Between Fin and Source/Drain Region App 20200006548 - Chin; Chih-Yun ; et al.	2020-01-02
Interfacial Layer Between Fin and Source/Drain Region App 20190378920 - Chin; Chih-Yun ; et al.	2019-12-12
Interfacial layer between fin and source/drain region Grant 10,483,396 - Chin , et al. Nov	2019-11-19
Supportive Layer in Source/Drains of FinFET Devices App 20190319098 - TAI; Roger ; et al.	2019-10-17
V-shape Recess Profile For Embedded Source/drain Epitaxy App 20180337283 - Li; Chii-Horng ; et al.	2018-11-22
V-shape recess profile for embedded source/drain epitaxy Grant 10,038,095 - Li , et al. July 31, 2	2018-07-31
V-Shape Recess Profile for Embedded Source/Drain Epitaxy App 20170222053 - Li; Chii-Horng ; et al.	2017-08-03

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