Synplicity, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Synplicity, Inc..The latest application filed is for "methods and apparatuses for designing integrated circuits".

Company Profile

0.55.1

Synplicity, Inc. - Sunnyvale CA
Synplicity, Inc. -

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Method and system for debug and test using replicated logic Grant 7,398,445 - Ng , et al. July 8, 2	2008-07-08
Methods and apparatuses for automated circuit optimization and verification Grant 7,376,919 - McElvain , et al. May 20, 2	2008-05-20
Methods and apparatuses for thermal analysis based circuit design Grant 7,366,997 - Rahmat , et al. April 29, 2	2008-04-29
Method and user interface for debugging an electronic system Grant 7,356,786 - Schubert , et al. April 8, 2	2008-04-08
Method and apparatus for placement and routing cells on integrated circuit chips Grant 7,350,173 - Ang , et al. March 25, 2	2008-03-25
Methods and apparatuses for transient analyses of circuits Grant 7,278,120 - Rahmat , et al. October 2, 2	2007-10-02
Methods and apparatuses for designing integrated circuits Grant 7,275,233 - McElvain , et al. September 25, 2	2007-09-25
Method and apparatus for automated synthesis and optimization of datapaths Grant 7,263,673 - McElvain , et al. August 28, 2	2007-08-28
Method and apparatus for automated circuit design Grant 7,251,800 - McElvain , et al. July 31, 2	2007-07-31
Hardware/software co-debugging in a hardware description language Grant 7,240,303 - Schubert , et al. July 3, 2	2007-07-03
Method and apparatus for circuit partitioning and trace assignment in circuit design Grant 7,237,214 - Pandey , et al. June 26, 2	2007-06-26
Hardware-based HDL code coverage and design analysis Grant 7,222,315 - Schubert , et al. May 22, 2	2007-05-22
Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device Grant 7,217,887 - Ho May 15, 2	2007-05-15
Method and system for debugging using replicated logic and trigger logic Grant 7,213,216 - Ng , et al. May 1, 2	2007-05-01
Circuits with modular redundancy and methods and apparatuses for their automated synthesis Grant 7,200,822 - McElvain April 3, 2	2007-04-03
Method and apparatus for automated circuit design Grant 7,178,118 - Ramachandran , et al. February 13, 2	2007-02-13
Method and apparatus for circuit design and retiming Grant 7,162,704 - Oktem January 9, 2	2007-01-09
Reducing equivalence checking complexity using inverse function Grant 7,146,589 - Rampon , et al. December 5, 2	2006-12-05
Method and apparatus for circuit design and synthesis Grant 7,131,078 - Maheshwari , et al. October 31, 2	2006-10-31
Verification of digital circuitry using range generators Grant 7,117,463 - Graham , et al. October 3, 2	2006-10-03
Method and system for user-defined triggering logic in a hardware description language Grant 7,107,570 - Larouche , et al. September 12, 2	2006-09-12
Method and apparatus for automated synthesis of multi-channel circuits Grant 7,093,204 - Oktem , et al. August 15, 2	2006-08-15
Reducing clock skew in clock gating circuits Grant 7,082,582 - Borkovic , et al. July 25, 2	2006-07-25
Method and system for debugging an electronic system Grant 7,072,818 - Beardslee , et al. July 4, 2	2006-07-04
Hardware debugging in a hardware description language Grant 7,069,526 - Schubert , et al. June 27, 2	2006-06-27
Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer Grant 7,065,481 - Schubert , et al. June 20, 2	2006-06-20
Method and apparatus for parallel carry chains Grant 7,051,296 - McElvain May 23, 2	2006-05-23
Methods and apparatuses for designing integrated circuits Grant 7,010,769 - McElvain , et al. March 7, 2	2006-03-07
Method and apparatus for the design and analysis of digital circuits with time division multiplexing Grant 7,007,254 - Borkovic , et al. February 28, 2	2006-02-28
Methods and apparatuses for designing integrated circuits Grant 6,978,430 - McElvain , et al. December 20, 2	2005-12-20
Method and apparatus to estimate delay for logic circuit optimization Grant 6,973,632 - Brahme , et al. December 6, 2	2005-12-06
Method and apparatus for resetable memory and design approach for same Grant 6,934,183 - Seshadri , et al. August 23, 2	2005-08-23
Design instrumentation circuitry Grant 6,931,572 - Schubert , et al. August 16, 2	2005-08-16
Hardware debugging in a hardware description language Grant 6,904,577 - Schubert , et al. June 7, 2	2005-06-07
Method and system for debugging using replicated logic Grant 6,904,576 - Ng , et al. June 7, 2	2005-06-07
Method and apparatus for resetable memory and design approach for same Grant 6,836,420 - Seshadri , et al. December 28, 2	2004-12-28
Method and user interface for debugging an electronic system Grant 6,823,497 - Schubert , et al. November 23, 2	2004-11-23
Method and apparatus for parallel carry chains Grant 6,807,556 - McElvain October 19, 2	2004-10-19
Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device Grant 6,734,472 - Ho May 11, 2	2004-05-11
Method and apparatus for invalid state detection Grant 6,735,743 - McElvain May 11, 2	2004-05-11
Local naming for HDL compilation Grant 6,732,350 - Falk May 4, 2	2004-05-04
Methods and apparatuses for designing integrated circuits using automatic reallocation techniques Grant 6,711,729 - McElvain , et al. March 23, 2	2004-03-23
Methods and apparatuses for checking equivalence of circuits Grant 6,691,286 - McElvain , et al. February 10, 2	2004-02-10
Methods and apparatuses for non-equivalence checking of circuits with subspace Grant 6,687,882 - McElvain , et al. February 3, 2	2004-02-03
Methods and apparatuses for designing integrated circuits Grant 6,668,364 - McElvain , et al. December 23, 2	2003-12-23
Reducing clock skew in clock gating circuits Grant 6,643,829 - Borkovic , et al. November 4, 2	2003-11-04
Transforming a circuit having loop structure and tri-state element using replication Grant 6,618,835 - Garlapati , et al. September 9, 2	2003-09-09
Method and system for providing an electronic system design with enhanced debugging capabilities Grant 6,618,839 - Beardslee , et al. September 9, 2	2003-09-09
Hardware debugging in a hardware description language Grant 6,581,191 - Schubert , et al. June 17, 2	2003-06-17
Methods and apparatuses for designing integrated circuits Grant 6,519,754 - McElvain , et al. February 11, 2	2003-02-11
Local naming for HDL compilation Grant 6,519,742 - Falk February 11, 2	2003-02-11
Methods and apparatuses for designing integrated circuits App 20020194572 - McElvain, Kenneth S. ; et al.	2002-12-19
Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis Grant 6,449,762 - McElvain September 10, 2	2002-09-10
Methods and apparatuses for designing integrated circuits Grant 6,438,735 - McElvain , et al. August 20, 2	2002-08-20
Method and apparatus for invalid state detection Grant 6,389,586 - McElvain May 14, 2	2002-05-14
Methods and apparatuses for automatic extraction of finite state machines Grant 6,182,268 - McElvain January 30, 2	2001-01-30

Company Registrations

NCAGE Code	07FU2	SYNPLICITY INC.
CAGE Code	07FU2	SYNPLICITY, INC.
SEC	0001027362	SYNPLICITY INC of CALIFORNIA