Syed; Ahmer
Patent Applications and Registrations
Patent applications and USPTO patent grants for Syed; Ahmer.The latest application filed is for "integrated device comprising bump on exposed redistribution interconnect".
- Syed; Ahmer - Chandler AZ
- Syed; Ahmer - Rancho Santa Fe CA
| Patent | Date |
|---|---|
| Robust pillar structure for semicondcutor device contacts Grant 10,236,268 - Dhandapani , et al. | 2019-03-19 |
| Integrated Device Comprising Bump On Exposed Redistribution Interconnect App 20180331061 - He; Dongming ; et al. | 2018-11-15 |
| Robust pillar structure for semicondcutor device contacts Grant 9,484,291 - Dhandapani , et al. November 1, 2 | 2016-11-01 |
| Stacked and staggered die MEMS package and method Grant 9,013,011 - Kuo , et al. April 21, 2 | 2015-04-21 |
| Method for controlling molding compound geometry around a semiconductor die Grant 8,912,051 - Syed , et al. December 16, 2 | 2014-12-16 |
| Edge mount semiconductor package Grant 8,217,507 - Galloway , et al. July 10, 2 | 2012-07-10 |
| Lead frame with plated end leads Grant 7,183,630 - Fogelson , et al. February 27, 2 | 2007-02-27 |
| Reduced copper lead frame for saw-singulated chip package Grant 6,885,086 - Fogelson , et al. April 26, 2 | 2005-04-26 |
| Lead frame with plated end leads Grant 6,608,366 - Fogelson , et al. August 19, 2 | 2003-08-19 |
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