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name:-0.01326584815979
name:-0.019374847412109
name:-0.0013160705566406
Swarbrick; Ian Patent Filings

Swarbrick; Ian

Patent Applications and Registrations

Patent applications and USPTO patent grants for Swarbrick; Ian.The latest application filed is for "dimm ssd addressing performance techniques".

Company Profile
1.18.10
  • Swarbrick; Ian - Santa Clara CA
  • Swarbrick; Ian - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
DIMM SSD Addressing performance techniques
Grant 10,503,657 - Hanson , et al. Dec
2019-12-10
XOR-based scrambler/descrambler for SSD communication protocols
Grant 10,121,013 - Chang , et al. November 6, 2
2018-11-06
Dimm Ssd Addressing Performance Techniques
App 20180239711 - HANSON; Craig ;   et al.
2018-08-23
DIMM SSD addressing performance techniques
Grant 10,031,674 - Hanson , et al. July 24, 2
2018-07-24
I/O channel scrambling/ECC disassociated communication protocol
Grant 10,025,747 - Swarbrick , et al. July 17, 2
2018-07-17
Dimm Ssd Addressing Performance Techniques
App 20170102873 - HANSON; Craig ;   et al.
2017-04-13
Fast Link Wake-up In Serial-based Io Fabrics
App 20160363986 - SWARBRICK; Ian ;   et al.
2016-12-15
Dram Memory Channel Scrambling/ecc Disassociated Communication
App 20160328156 - SWARBRICK; Ian ;   et al.
2016-11-10
Xor-based Scrambler/descrambler For Ssd Communication Protocols
App 20160328567 - Chang; Chihjen ;   et al.
2016-11-10
Bi-domain bridge enhanced systems and communication methods
Grant 9,489,304 - Swarbrick , et al. November 8, 2
2016-11-08
Chip-to-chip communications
Grant 9,264,368 - Swarbrick , et al. February 16, 2
2016-02-16
Adaptive voltage scaling using a delay line
Grant 9,264,030 - Zhu , et al. February 16, 2
2016-02-16
Method for inter-chip and intra-chip addressing using port identifiers and address mapping
Grant 8,949,474 - Swarbrick , et al. February 3, 2
2015-02-03
Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers
Grant 8,826,047 - Zhu , et al. September 2, 2
2014-09-02
Adaptive voltage scaling using a delay line
Grant 8,717,089 - Zhu , et al. May 6, 2
2014-05-06
Adaptive voltage scaling using a delay line
Grant 8,519,781 - Zhu , et al. August 27, 2
2013-08-27
Chip-to-chip Communications
App 20130195210 - Swarbrick; Ian ;   et al.
2013-08-01
System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device
Grant 8,448,001 - Zhu , et al. May 21, 2
2013-05-21
Adaptive voltage scaling using a delay line
Grant 8,378,738 - Zhu , et al. February 19, 2
2013-02-19
Clock distribution system
Grant 7,290,162 - Swarbrick , et al. October 30, 2
2007-10-30
Clock distribution system
App 20040130367 - Swarbrick, Ian ;   et al.
2004-07-08
Interconnection system
App 20040114609 - Swarbrick, Ian ;   et al.
2004-06-17

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