Swamynathan; Chethan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Swamynathan; Chethan.The latest application filed is for "circuit and layout techniques for flop tray area and power otimization".
- Swamynathan; Chethan - Bangalore IN
| Patent | Date |
|---|---|
| Integrated device comprising device level cells with variable sizes for heat dissipation around hotspots Grant 10,141,297 - Jain , et al. Nov | 2018-11-27 |
| Circuit and layout techniques for flop tray area and power otimization Grant 9,024,658 - Shah , et al. May 5, 2 | 2015-05-05 |
| Circuit And Layout Techniques For Flop Tray Area And Power Otimization App 20140359385 - Shah; Jay Madhukar ; et al. | 2014-12-04 |
| Standard cell architecture using double poly patterning for multi VT devices Grant 8,610,176 - Patel , et al. December 17, 2 | 2013-12-17 |
| Area Efficient Gridded Polysilicon Layouts App 20130032885 - Swamynathan; Chethan ; et al. | 2013-02-07 |
| Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices App 20120180016 - Chidambaram; PR ; et al. | 2012-07-12 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 