Suvarna; Puneet Harischandra

Patent Applications and Registrations

Patent applications and USPTO patent grants for Suvarna; Puneet Harischandra.The latest application filed is for "vertically stacked complementary-fet device with independent gate control".

Company Profile

12.13.10

Suvarna; Puneet Harischandra - Menands NY
SUVARNA; Puneet Harischandra - Albany NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vertically stacked complementary-FET device with independent gate control Grant 10,784,171 - Frougier , et al. Sept	2020-09-22
Vertically Stacked Complementary-fet Device With Independent Gate Control App 20200035569 - Frougier; Julien ; et al.	2020-01-30
Vertically stacked complementary-FET device with independent gate control Grant 10,510,622 - Frougier , et al. Dec	2019-12-17
Vertical field effect transistor with self-aligned contacts Grant 10,497,798 - Xie , et al. De	2019-12-03
Negative capacitance integration through a gate contact Grant 10,446,659 - Bentley , et al. Oc	2019-10-15
Circuits based on complementary field-effect transistors Grant 10,418,449 - Paul , et al. Sept	2019-09-17
Vertical Field Effect Transistor With Self-aligned Contacts App 20190252267 - Xie; Ruilong ; et al.	2019-08-15
Circuits Based On Complementary Field-effect Transistors App 20190214469 - Paul; Bipul C. ; et al.	2019-07-11
Methods of forming bottom and top source/drain regions on a vertical transistor device Grant 10,347,745 - Suvarna , et al. July 9, 2	2019-07-09
Negative capacitance matching in gate electrode structures Grant 10,332,969 - Galatage , et al.	2019-06-25
Method of forming vertical FinFET device having self-aligned contacts Grant 10,312,154 - Xie , et al.	2019-06-04
Method of forming complementary nano-sheet/wire transistor devices with same depth contacts Grant 10,304,833 - Suvarna , et al.	2019-05-28
Negative Capacitance Integration Through A Gate Contact App 20190115444 - BENTLEY; Steven ; et al.	2019-04-18
Negative Capacitance Matching In Gate Electrode Structures App 20190115437 - Galatage; Rohit ; et al.	2019-04-18
Self-aligned Contacts For Vertical Field Effect Transistor Cell Height Scaling App 20190088764 - XIE; Ruilong ; et al.	2019-03-21
Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process Grant 10,236,379 - Bentley , et al.	2019-03-19
Vertical transport field effect transistors Grant 10,170,617 - Kim , et al. J	2019-01-01
Negative capacitance matching in gate electrode structures Grant 10,141,414 - Galatage , et al. Nov	2018-11-27
Vertical Fet With Self-aligned Source/drain Regions And Gate Length Based On Channel Epitaxial Growth Process App 20180331213 - Bentley; Steven ; et al.	2018-11-15
Vertical Transport Field Effect Transistors App 20180226505 - KIM; Jiseok ; et al.	2018-08-09
Vertical Transistors Stressed From Various Directions App 20180108776 - SUVARNA; Puneet Harischandra	2018-04-19
Vertical transistors stressed from various directions Grant 9,947,789 - Suvarna April 17, 2	2018-04-17
Methods Of Forming Bottom And Top Source/drain Regions On A Vertical Transistor Device App 20180083121 - Suvarna; Puneet Harischandra ; et al.	2018-03-22

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