loadpatents
name:-0.01818585395813
name:-0.020658016204834
name:-0.0015380382537842
Surisetty; Charan Veera Venkata Satya Patent Filings

Surisetty; Charan Veera Venkata Satya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Surisetty; Charan Veera Venkata Satya.The latest application filed is for "nanosheet isolation for bulk cmos non-planar devices".

Company Profile
1.18.15
  • Surisetty; Charan Veera Venkata Satya - Clifton Park NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Nanosheet isolation for bulk CMOS non-planar devices
Grant 10,559,654 - Pranatharthiharan , et al. Feb
2020-02-11
Semiconductor structure containing low-resistance source and drain contacts
Grant 10,249,624 - Ok , et al.
2019-04-02
Semiconductor device with gate structures having low-K spacers on sidewalls and electrical contacts therebetween
Grant 9,966,374 - Cheng , et al. May 8, 2
2018-05-08
Nanosheet Isolation For Bulk Cmos Non-planar Devices
App 20180090566 - Pranatharthiharan; Balasubramanian ;   et al.
2018-03-29
Improving channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
Grant 9,905,421 - Ok , et al. February 27, 2
2018-02-27
Nanosheet isolation for bulk CMOS non-planar devices
Grant 9,871,099 - Pranatharthiharan , et al. January 16, 2
2018-01-16
Semiconductor Structure Containing Low-resistance Source And Drain Contacts
App 20180012892 - Ok; Injo ;   et al.
2018-01-11
Semiconductor structure containing low-resistance source and drain contacts
Grant 9,768,173 - Ok , et al. September 19, 2
2017-09-19
Stable contact on one-sided gate tie-down structure
Grant 9,685,340 - Ok , et al. June 20, 2
2017-06-20
Improving Channel Strain And Controlling Lateral Epitaxial Growth Of The Source And Drain In Finfet Devices
App 20170154774 - Ok; Injo ;   et al.
2017-06-01
Nanosheet Isolation For Bulk Cmos Non-planar Devices
App 20170133459 - Pranatharthiharan; Balasubramanian ;   et al.
2017-05-11
Forming dual contact silicide using metal multi-layer and ion beam mixing
Grant 9,595,592 - Ok , et al. March 14, 2
2017-03-14
Stable Contact On One-sided Gate Tie-down Structure
App 20160379925 - Ok; Injo ;   et al.
2016-12-29
Low resistance replacement metal gate structure
Grant 9,508,816 - Ok , et al. November 29, 2
2016-11-29
Semiconductor Structure Containing Low-resistance Source And Drain Contacts
App 20160336323 - Ok; Injo ;   et al.
2016-11-17
Capacitance reduction for advanced technology nodes
Grant 9,484,401 - Ok , et al. November 1, 2
2016-11-01
Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
Grant 9,461,168 - Ok , et al. October 4, 2
2016-10-04
Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
Grant 9,431,486 - Ok , et al. August 30, 2
2016-08-30
Semiconductor Device With Low-k Spacer
App 20160225766 - Cheng; Kangguo ;   et al.
2016-08-04
Semiconductor structure containing low-resistance source and drain contacts
Grant 9,406,568 - Ok , et al. August 2, 2
2016-08-02
Low Resistance Replacement Metal Gate Structure
App 20160163809 - Ok; Injo ;   et al.
2016-06-09
Semiconductor Structure Containing Low-resistance Source And Drain Contacts
App 20160148846 - Ok; Injo ;   et al.
2016-05-26
Capacitance Reduction For Advanced Technology Nodes
App 20160148999 - Ok; Injo ;   et al.
2016-05-26
Methods for replacing gate sidewall materials with a low-k spacer
Grant 9,349,835 - Cheng , et al. May 24, 2
2016-05-24
Low resistance replacement metal gate structure
Grant 9,305,923 - Ok , et al. April 5, 2
2016-04-05
Integrated circuits having gate cap protection and methods of forming the same
Grant 9,269,611 - Pham , et al. February 23, 2
2016-02-23
Integrated Circuits Having Gate Cap Protection And Methods Of Forming The Same
App 20150206844 - Pham; Daniel Thanh Khae ;   et al.
2015-07-23
Semiconductor fabrication method using stop layer
Grant 9,087,796 - Adam , et al. July 21, 2
2015-07-21
Semiconductor Device With Low-k Spacer
App 20150076606 - Cheng; Kangguo ;   et al.
2015-03-19
Semiconductor Fabrication Method Using Stop Layer
App 20140242797 - Adam; Thomas N. ;   et al.
2014-08-28
Methods of forming replacement gate structures on semiconductor devices and the resulting device
Grant 8,772,101 - Xie , et al. July 8, 2
2014-07-08
Dielectric Cap Layer For Replacement Gate With Self-aligned Contact
App 20140134836 - PRANATHARTHIHARAN; BALASUBRAMANIAN ;   et al.
2014-05-15
Methods Of Forming Replacement Gate Structures On Semiconductor Devices And The Resulting Device
App 20140124841 - Xie; Ruilong ;   et al.
2014-05-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed