Surisetty; Charan V. V. S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Surisetty; Charan V. V. S..The latest application filed is for "method and structure of improving contact resistance for passive and long channel devices".

Company Profile

11.38.37

Surisetty; Charan V. V. S. - Clifton Park NY
Surisetty; Charan V. V. S. - Cliffton Park NY
Surisetty; Charan V. V. S. - Albany NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and structure of improving contact resistance for passive and long channel devices Grant 11,038,055 - Ok , et al. June 15, 2	2021-06-15
Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack Grant 10,937,861 - Ok , et al. March 2, 2	2021-03-02
Simultaneously fabricating a high voltage transistor and a FinFET Grant 10,811,410 - Cheng , et al. October 20, 2	2020-10-20
Spacer for trench epitaxial structures Grant 10,790,284 - Ok , et al. September 29, 2	2020-09-29
Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack Grant 10,763,326 - Ok , et al. Sep	2020-09-01
Spacer for trench epitaxial structures Grant 10,741,559 - Ok , et al. A	2020-08-11
Self-aligned low dielectric constant gate cap and a method of forming the same Grant 10,699,951 - Pranatharthiharan , et al.	2020-06-30
Contact resistance reduction for advanced technology nodes Grant 10,629,721 - Ok , et al.	2020-04-21
Method And Structure Of Improving Contact Resistance For Passive And Long Channel Devices App 20190305132 - Ok; Injo ; et al.	2019-10-03
Spacer For Trench Epitaxial Structures App 20190296015 - OK; Injo ; et al.	2019-09-26
Simultaneously Fabricating A High Voltage Transistor And A Finfet App 20190287968 - Cheng; Kangguo ; et al.	2019-09-19
Spacer For Trench Epitaxial Structures App 20190279983 - OK; Injo ; et al.	2019-09-12
Method and structure of improving contact resistance for passive and long channel devices Grant 10,396,200 - Ok , et al. A	2019-08-27
Semiconductor Structures Including Middle-of-line (mol) Capacitance Reduction For Self-aligned Contact In Gate Stack App 20190259831 - Ok; Injo ; et al.	2019-08-22
FET trench dipole formation Grant 10,361,203 - Ok , et al.	2019-07-23
Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack Grant 10,355,080 - Ok , et al. July 16, 2	2019-07-16
Forming spacer for trench epitaxial structures Grant 10,347,632 - Ok , et al. July 9, 2	2019-07-09
Spacer for trench epitaxial structures Grant 10,347,633 - Ok , et al. July 9, 2	2019-07-09
Simultaneously fabricating a high voltage transistor and a FinFET Grant 10,347,628 - Cheng , et al. July 9, 2	2019-07-09
Self-aligned local interconnect technology Grant 10,325,848 - Greene , et al.	2019-06-18
Middle-of-line (mol) Capacitance Reduction For Self-aligned Contact In Gate Stack App 20190157388 - Ok; Injo ; et al.	2019-05-23
Contact Resistance Reduction For Advanced Technology Nodes App 20190148535 - Ok; Injo ; et al.	2019-05-16
Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack Grant 10,256,296 - Ok , et al. April 9, 2	2019-04-09
FinFETs with high quality source/drain structures Grant 10,243,044 - Cheng , et al.	2019-03-26
Self-aligned local interconnect technology Grant 10,236,253 - Greene , et al.	2019-03-19
Self-aligned low dielectric constant gate cap and a method of forming the same Grant 10,229,852 - Pranatharthiharan , et al.	2019-03-12
Self-aligned Local Interconnect Technology App 20190013268 - Greene; Andrew M. ; et al.	2019-01-10
Method And Structure Of Improving Contact Resistance For Passive And Long Channel Devices App 20180294356 - Ok; Injo ; et al.	2018-10-11
Semiconductor device with low-K gate cap and self-aligned contact Grant 10,084,050 - Cheng , et al. September 25, 2	2018-09-25
Spacer For Trench Epitaxial Structures App 20180254274 - OK; Injo ; et al.	2018-09-06
Spacer For Trench Epitaxial Structures App 20180254275 - OK; Injo ; et al.	2018-09-06
Method and structure of improving contact resistance for passive and long channel devices Grant 10,043,904 - Ok , et al. August 7, 2	2018-08-07
Spacer for trench epitaxial structures Grant 10,020,306 - Ok , et al. July 10, 2	2018-07-10
Self-aligned Low Dielectric Constant Gate Cap And A Method Of Forming The Same App 20180090375 - Pranatharthiharan; Balasubramanian ; et al.	2018-03-29
Self-aligned Low Dielectric Constant Gate Cap And A Method Of Forming The Same App 20180082895 - Pranatharthiharan; Balasubramanian ; et al.	2018-03-22
Self-aligned low dielectric constant gate cap and a method of forming the same Grant 9,905,463 - Pranatharthiharan , et al. February 27, 2	2018-02-27
Method And Structure Of Improving Contact Resistance For Passive And Long Channel Devices App 20180053851 - Ok; Injo ; et al.	2018-02-22
Simultaneously fabricating a high voltage transistor and a finFET Grant 9,899,378 - Cheng , et al. February 20, 2	2018-02-20
Method and structure of improving contact resistance for passive and long channel devices Grant 9,887,289 - Ok , et al. February 6, 2	2018-02-06
FINFETs WITH HIGH QUALITY SOURCE/DRAIN STRUCTURES App 20180033857 - Cheng; Kangguo ; et al.	2018-02-01
Simultaneously Fabricating A High Voltage Transistor And A Finfet App 20170373061 - Cheng; Kangguo ; et al.	2017-12-28
Fet Trench Dipole Formation App 20170330802 - Ok; Injo ; et al.	2017-11-16
Forming stressed epitaxial layers between gates separated by different pitches Grant 9,818,873 - Alptekin , et al. November 14, 2	2017-11-14
FET trench dipole formation Grant 9,799,654 - Ok , et al. October 24, 2	2017-10-24
FINFETs with high quality source/drain structures Grant 9,799,730 - Cheng , et al. October 24, 2	2017-10-24
Strained FinFET by epitaxial stressor independent of gate pitch Grant 9,773,905 - Cheng , et al. September 26, 2	2017-09-26
Self-aligned Local Interconnect Technology App 20170221808 - Greene; Andrew M. ; et al.	2017-08-03
Self-aligned local interconnect technology Grant 9,698,101 - Greene , et al. July 4, 2	2017-07-04
Inter-level dielectric layer in replacement metal gates and resistor fabrication Grant 9,685,434 - Cheng , et al. June 20, 2	2017-06-20
Method And Structure Of Improving Contact Resistance For Passive And Long Channel Devices App 20170170315 - Ok; Injo ; et al.	2017-06-15
Self-aligned Low Dielectric Constant Gate Cap And A Method Of Forming The Same App 20170170068 - Pranatharthiharan; Balasubramanian ; et al.	2017-06-15
Simultaneously Fabricating A High Voltage Transistor And A Finfet App 20170170172 - Cheng; Kangguo ; et al.	2017-06-15
Contact Resistance Reduction For Advanced Technology Nodes App 20170162444 - Ok; Injo ; et al.	2017-06-08
Middle-of-line (mol) Capacitance Reduction For Self-aligned Contact In Gate Stack App 20170148874 - Ok; Injo ; et al.	2017-05-25
Semiconductor Structures Including Middle-of-line (mol) Capacitance Reduction For Self-aligned Contact In Gate Stack App 20170148662 - Ok; Injo ; et al.	2017-05-25
Strained FinFET by epitaxial stressor independent of gate pitch Grant 9,647,113 - Cheng , et al. May 9, 2	2017-05-09
Forming Stressed Epitaxial Layer Using Dummy Gates App 20170104100 - Alptekin; Emre ; et al.	2017-04-13
Spacer For Trench Epitaxial Structures App 20170103984 - Ok; Injo ; et al.	2017-04-13
Simultaneously fabricating a high voltage transistor and a finFET Grant 9,607,898 - Cheng , et al. March 28, 2	2017-03-28
Shallow trench isolation regions made from crystalline oxides Grant 9,589,827 - Cheng , et al. March 7, 2	2017-03-07
Self-aligned Local Interconnect Technology App 20170062325 - Greene; Andrew M. ; et al.	2017-03-02
Shallow Trench Isolation Regions Made From Crystalline Oxides App 20170025305 - Cheng; Kangguo ; et al.	2017-01-26
Fet Trench Dipole Formation App 20160372470 - Ok; Injo ; et al.	2016-12-22
FINFETs WITH HIGH QUALITY SOURCE/DRAIN STRUCTURES App 20160351662 - Cheng; Kangguo ; et al.	2016-12-01
Co-integration of different fin pitches for logic and analog devices Grant 9,397,006 - Ok , et al. July 19, 2	2016-07-19
Inter-level Dielectric Layer In Replacement Metal Gates And Resistor Fabrication App 20160172356 - Cheng; Kangguo ; et al.	2016-06-16
Double diamond shaped unmerged epitaxy for tall fins in tight pitch Grant 9,368,512 - Cheng , et al. June 14, 2	2016-06-14
Semiconductor Device With Low-k Gate Cap And Self-aligned Contact App 20160163808 - Cheng; Kangguo ; et al.	2016-06-09
Method of forming contact useful in replacement metal gate processing and related semiconductor structure Grant 9,337,094 - Pranatharthiharan , et al. May 10, 2	2016-05-10
Semiconductor device with low-k gate cap and self-aligned contact Grant 9,293,576 - Cheng , et al. March 22, 2	2016-03-22
Endpoint Determination Using Individually Measured Target Spectra App 20160033958 - Tsai; Stan ; et al.	2016-02-04
Shallow Trench Isolation Regions Made From Crystalline Oxides App 20150364361 - Cheng; Kangguo ; et al.	2015-12-17
STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH App 20150349123 - Cheng; Kangguo ; et al.	2015-12-03
Semiconductor Device With Low-k Gate Cap And Self-aligned Contact App 20150255556 - Cheng; Kangguo ; et al.	2015-09-10
STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH App 20150255543 - Cheng; Kangguo ; et al.	2015-09-10

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