Surisetty; Charan V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Surisetty; Charan V..The latest application filed is for "semiconductor structures including middle-of-line (mol) capacitance reduction for self-aligned contact in gate stack".

Company Profile

9.34.30

Surisetty; Charan V. - Clifton Park NY
Surisetty; Charan V. - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Structures Including Middle-of-line (mol) Capacitance Reduction For Self-aligned Contact In Gate Stack App 20210210596 - Ok; Injo ; et al.	2021-07-08
Minimizing Shorting Between Finfet Epitaxial Regions App 20210183856 - Cheng; Kangguo ; et al.	2021-06-17
Forming dual metallization interconnect structures in single metallization level Grant 11,037,875 - Amanapu , et al. June 15, 2	2021-06-15
Forming dual metallization interconnect structures in single metallization level Grant 11,031,337 - Amanapu , et al. June 8, 2	2021-06-08
Minimize middle-of-line contact line shorts Grant 11,011,429 - Ok , et al. May 18, 2	2021-05-18
Minimizing shorting between FinFET epitaxial regions Grant 10,923,471 - Cheng , et al. February 16, 2	2021-02-16
Silicon residue removal in nanosheet transistors Grant 10,896,816 - Bi , et al. January 19, 2	2021-01-19
Minimize Middle-of-line Contact Line Shorts App 20200402860 - Ok; Injo ; et al.	2020-12-24
Minimize middle-of-line contact line shorts Grant 10,804,159 - Ok , et al. October 13, 2	2020-10-13
Minimize Middle-of-line Contact Line Shorts App 20200051866 - Ok; Injo ; et al.	2020-02-13
Forming dual metallization interconnect structures in single metallization level Grant 10,559,530 - Amanapu , et al. Feb	2020-02-11
Minimize middle-of-line contact line shorts Grant 10,490,454 - Ok , et al. Nov	2019-11-26
Forming Dual Metallization Interconnect Structures In Single Metallization Level App 20190311986 - Amanapu; Hari P. ; et al.	2019-10-10
Semiconductor device replacement metal gate with gate cut last in RMG Grant 10,381,458 - Greene , et al. A	2019-08-13
Forming Dual Metallization Interconnect Structures In Single Metallization Level App 20190221519 - Amanapu; Hari P. ; et al.	2019-07-18
Minimizing Shorting Between Finfet Epitaxial Regions App 20190206865 - Cheng; Kangguo ; et al.	2019-07-04
Forming Dual Metallization Interconnect Structures In Single Metallization Level App 20190198444 - Amanapu; Hari P. ; et al.	2019-06-27
Minimizing shorting between FinFET epitaxial regions Grant 10,276,569 - Cheng , et al.	2019-04-30
Silicon Residue Removal In Nanosheet Transistors App 20190096669 - Bi; Zhenxing ; et al.	2019-03-28
FinFET device formed by a replacement metal-gate method including a gate cut-last step Grant 10,177,240 - Greene , et al. J	2019-01-08
Minimize Middle-of-line Contact Line Shorts App 20180323109 - OK; Injo ; et al.	2018-11-08
Minimize middle-of-line contact line shorts Grant 10,074,569 - Ok , et al. September 11, 2	2018-09-11
Minimizing Shorting Between Finfet Epitaxial Regions App 20180204837 - Cheng; Kangguo ; et al.	2018-07-19
Self heating reduction for analog radio frequency (RF) device Grant 10,014,295 - Ok , et al. July 3, 2	2018-07-03
Self heating reduction for analog radio frequency (RF) device Grant 10,014,220 - Ok , et al. July 3, 2	2018-07-03
Minimizing shorting between FinFET epitaxial regions Grant 9,985,024 - Cheng , et al. May 29, 2	2018-05-29
Preventing shorting between source and/or drain contacts and gate Grant 9,972,620 - Surisetty , et al. May 15, 2	2018-05-15
Effective device formation for advanced technology nodes with aggressive fin-pitch scaling Grant 9,953,976 - Ok , et al. April 24, 2	2018-04-24
III-V semiconductor CMOS FinFET device Grant 9,917,089 - Jagannathan , et al. March 13, 2	2018-03-13
Preventing Shorting Between Source And/or Drain Contacts And Gate App 20180047727 - SURISETTY; Charan V. ; et al.	2018-02-15
Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture Grant 9,893,085 - Ok , et al. February 13, 2	2018-02-13
Minimizing shorting between FinFET epitaxial regions Grant 9,852,951 - Cheng , et al. December 26, 2	2017-12-26
Minimize Middle-of-line Contact Line Shorts App 20170323833 - Ok; Injo ; et al.	2017-11-09
Iii-v Semiconductor Cmos Finfet Device App 20170229459 - Jagannathan; Hemanth ; et al.	2017-08-10
Minimizing Shorting Between Finfet Epitaxial Regions App 20170229455 - Cheng; Kangguo ; et al.	2017-08-10
Integrated Circuit (ic) With Offset Gate Sidewall Contacts And Method Of Manufacture App 20170229479 - Ok; Injo ; et al.	2017-08-10
Almost defect-free active channel region Grant 9,728,626 - Schepis , et al. August 8, 2	2017-08-08
Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture Grant 9,704,760 - Ok , et al. July 11, 2	2017-07-11
Minimizing shorting between FinFET epitaxial regions Grant 9,704,753 - Cheng , et al. July 11, 2	2017-07-11
Self Heating Reduction For Analog Radio Frequency (rf) Device App 20170162567 - Ok; Injo ; et al.	2017-06-08
Self Heating Reduction For Analog Radio Frequency (rf) Device App 20170162445 - Ok; Injo ; et al.	2017-06-08
Minimize middle-of-line contact line shorts Grant 9,673,101 - Ok , et al. June 6, 2	2017-06-06
Effective Device Formation For Advanced Technology Nodes With Aggressive Fin-pitch Scaling App 20170148789 - Ok; Injo ; et al.	2017-05-25
Semiconductor device having reduced contact resistance Grant 9,627,322 - Ok , et al. April 18, 2	2017-04-18
Minimize Middle-of-line Contact Line Shorts App 20170092543 - Ok; Injo ; et al.	2017-03-30
Semiconductor Device Replacement Metal Gate With Gate Cut Last In Rmg App 20170084723 - Greene; Andrew M. ; et al.	2017-03-23
Semiconductor Device Replacement Metal Gate With Gate Cut Last In Rmg App 20170084463 - Greene; Andrew M. ; et al.	2017-03-23
Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication Grant 9,601,482 - Fogel , et al. March 21, 2	2017-03-21
Effective device formation for advanced technology nodes with aggressive fin-pitch scaling Grant 9,564,370 - Ok , et al. February 7, 2	2017-02-07
Integrated Circuit (ic) With Offset Gate Sidewall Contacts And Method Of Manufacture App 20160379893 - Ok; Injo ; et al.	2016-12-29
Self heating reduction for analog radio frequency (RF) device Grant 9,520,500 - Ok , et al. December 13, 2	2016-12-13
Minimizing Shorting Between Finfet Epitaxial Regions App 20160358824 - Cheng; Kangguo ; et al.	2016-12-08
III-V semiconductor CMOS FinFET device Grant 9,515,073 - Jagannathan , et al. December 6, 2	2016-12-06
Minimizing Shorting Between Finfet Epitaxial Regions App 20160315144 - CHENG; KANGGUO ; et al.	2016-10-27
Minimizing shorting between FinFET epitaxial regions Grant 9,443,853 - Cheng , et al. September 13, 2	2016-09-13
Semiconductor Device Having Reduced Contact Resistance App 20160148872 - Ok; Injo ; et al.	2016-05-26
Semiconductor device having reduced contact resistance Grant 9,275,901 - Ok , et al. March 1, 2	2016-03-01
Growing buffer layers in bulk finFET structures Grant 9,159,811 - Cheng , et al. October 13, 2	2015-10-13
Growing Buffer Layers In Bulk Finfet Structures App 20150171193 - Cheng; Kangguo ; et al.	2015-06-18
Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors Grant 9,059,164 - Cheng , et al. June 16, 2	2015-06-16
Embedded Interlevel Dielectric Barrier Layers For Replacement Metal Gate Field Effect Transistors App 20150108589 - Cheng; Kangguo ; et al.	2015-04-23
Reducing Gate Height Variation In Rmg Process App 20150111373 - Cote; William J. ; et al.	2015-04-23
Borderless Contacts For Semiconductor Transistors App 20140162452 - Cheng; Kangguo ; et al.	2014-06-12
Borderless contacts for semiconductor transistors Grant 8,728,927 - Cheng , et al. May 20, 2	2014-05-20