Sundaresan; Ravishankar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sundaresan; Ravishankar.The latest application filed is for "method of forming asymmetrical polysilicon thin film transistor".

Company Profile

0.18.3

Sundaresan; Ravishankar - Plano TX
Sundaresan; Ravishankar - Garland TX
Sundaresan; Ravishankar - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Sram cell fabrication with interlevel Dielectric planarization Grant RE41,670 - Nguyen , et al. September 14, 2	2010-09-14
Method and interlevel dielectric structure for improved metal step coverage Grant 6,812,142 - Nguyen , et al. November 2, 2	2004-11-02
Method of forming asymmetrical polysilicon thin film transistor App 20040178446 - Sundaresan, Ravishankar	2004-09-16
Method of fabricating a one-sided polysilicon thin film transistor Grant 6,753,576 - Sundaresan June 22, 2	2004-06-22
Method to form shallow junction transistors while eliminating shorts due to junction spiking App 20020011629 - Chan, Lap ; et al.	2002-01-31
Method to form shallow junction transistors while eliminating shorts due to junction spiking App 20020003264 - Chan, Lap ; et al.	2002-01-10
Method to form shallow junction transistors while eliminating shorts due to junction spiking Grant 6,297,109 - Chan , et al. October 2, 2	2001-10-02
SRAM cell with thin film transistor using two polysilicon layers Grant 6,107,642 - Sundaresan August 22, 2	2000-08-22
Method of manufacture of self-aligned JFET Grant 5,702,987 - Chen , et al. December 30, 1	1997-12-30
Sidewall doping technique for SOI transistors Grant 5,346,839 - Sundaresan September 13, 1	1994-09-13
Method of forming a gate overlap LDD structure Grant 5,304,504 - Wei , et al. April 19, 1	1994-04-19
Stacked CMOS SRAM cell with polysilicon transistor load Grant 5,298,782 - Sundaresan March 29, 1	1994-03-29
SOI BICMOS process Grant 5,294,823 - Eklund , et al. March 15, 1	1994-03-15
Sidewall doping technique for SOI transistors Grant 5,292,670 - Sundaresan March 8, 1	1994-03-08
Elevated CMOS Grant 5,293,053 - Malhi , et al. * March 8, 1	1994-03-08
SOI BICMOS process Grant 5,102,809 - Eklund , et al. April 7, 1	1992-04-07
Elevated CMOS Grant 5,072,276 - Malhi , et al. December 10, 1	1991-12-10
Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors Grant 5,016,070 - Sundaresan May 14, 1	1991-05-14
Masking scheme for silicon dioxide mesa formation Grant 4,950,618 - Sundaresan , et al. August 21, 1	1990-08-21
Method for fabricating stacked CMOS transistors with a self-aligned silicide process Grant 4,656,731 - Lam , et al. April 14, 1	1987-04-14
Method for fabricating stacked CMOS structures Grant 4,628,589 - Sundaresan December 16, 1	1986-12-16

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