| Patent | Date |
|---|
CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor
Grant 6,759,717 - Sagarwala , et al. July 6, 2 | 2004-07-06 |
Method to form a self-aligned CMOS inverter using vertical device integration
Grant 6,747,314 - Sundaresan , et al. June 8, 2 | 2004-06-08 |
Method for forming variable-K gate dielectric
Grant 6,709,934 - Lee , et al. March 23, 2 | 2004-03-23 |
Method to form a self-aligned CMOS inverter using vertical device integration
App 20030075758 - Sundaresan, Ravi ; et al. | 2003-04-24 |
Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel
Grant 6,544,824 - Pradeep , et al. April 8, 2 | 2003-04-08 |
Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area
App 20030017710 - Yang, Pan ; et al. | 2003-01-23 |
Method for forming variable-K gate dielectric
App 20020173106 - Lee, James Yong Meng ; et al. | 2002-11-21 |
Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
Grant 6,468,877 - Pradeep , et al. October 22, 2 | 2002-10-22 |
Method to form a self-aligned CMOS inverter using vertical device integration
Grant 6,461,900 - Sundaresan , et al. October 8, 2 | 2002-10-08 |
Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation
Grant 6,436,770 - Leung , et al. August 20, 2 | 2002-08-20 |
Method for forming variable-K gate dielectric
App 20020100947 - Lee, James Yong Meng ; et al. | 2002-08-01 |
Method For Fabricating A Self Aligned S/d Cmos Device On Insulated Layer By Forming A Trench Along The Sti And Fill With Oxide
App 20020102798 - Zheng, Jia Zhen ; et al. | 2002-08-01 |
Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers
App 20020102784 - Lee, James Yong Meng ; et al. | 2002-08-01 |
Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
App 20020098655 - Zheng, Jia Zhen ; et al. | 2002-07-25 |
Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge
Grant 6,417,056 - Quek , et al. July 9, 2 | 2002-07-09 |
Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide
Grant 6,417,054 - Zheng , et al. July 9, 2 | 2002-07-09 |
Method to form a low parasitic capacitance pseudo-SOI CMOS device
Grant 6,403,485 - Quek , et al. June 11, 2 | 2002-06-11 |
Method to form a recessed source drain on a trench side wall with a replacement gate technique
Grant 6,380,088 - Chan , et al. April 30, 2 | 2002-04-30 |
Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance
Grant 6,372,569 - Lee , et al. April 16, 2 | 2002-04-16 |
Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
Grant 6,313,008 - Leung , et al. November 6, 2 | 2001-11-06 |
Method to form smaller channel with CMOS device by isotropic etching of the gate materials
Grant 6,306,715 - Chan , et al. October 23, 2 | 2001-10-23 |
Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials
Grant 6,300,177 - Sundaresan , et al. October 9, 2 | 2001-10-09 |
CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor
App 20010009796 - Sagarwala, Pervez Hassan ; et al. | 2001-07-26 |
Method of forming contact to polysilicon gate for MOS devices
Grant 6,261,935 - See , et al. July 17, 2 | 2001-07-17 |
Process having high tolerance to buried contact mask misalignment by using a PSG spacer
Grant 5,742,088 - Pan , et al. April 21, 1 | 1998-04-21 |
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