| Patent | Date |
|---|
Power regulating apparatus
Grant 8,624,435 - Tsai , et al. January 7, 2 | 2014-01-07 |
Network Interface Based On Detection Of Input Combination Interface
App 20130086284 - Shaver; Charles N. ; et al. | 2013-04-04 |
Power Regulating Apparatus
App 20120268973 - TSAI; TSAO-CHING ; et al. | 2012-10-25 |
High density plasma chemical vapor deposition process
Grant 8,062,536 - Liu , et al. November 22, 2 | 2011-11-22 |
High Density Plasma Chemical Vapor Deposition Process
App 20100173490 - Liu; Chih-Chien ; et al. | 2010-07-08 |
Programmable Array Module
App 20100123477 - Sun; Shih-Wei | 2010-05-20 |
High density plasma chemical vapor deposition process
Grant 7,718,079 - Liu , et al. May 18, 2 | 2010-05-18 |
CMOS device and fabricating method thereof
Grant 7,615,434 - Sun , et al. November 10, 2 | 2009-11-10 |
High density plasma chemical vapor deposition process
Grant 7,514,014 - Liu , et al. April 7, 2 | 2009-04-07 |
Method Of Manufacturing A Mos Transistor Device
App 20080242020 - Chen; Jei-Ming ; et al. | 2008-10-02 |
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
Grant 7,378,740 - Yew , et al. May 27, 2 | 2008-05-27 |
CMOS device and fabricating method thereof
App 20070238238 - Sun; Shih-Wei ; et al. | 2007-10-11 |
High density plasma chemical vapor deposition process
Grant 7,271,101 - Liu , et al. September 18, 2 | 2007-09-18 |
High density plasma chemical vapor deposition process
Grant 7,078,346 - Liu , et al. July 18, 2 | 2006-07-18 |
High density plasma chemical vapor deposition process
App 20060099824 - Liu; Chih-Chien ; et al. | 2006-05-11 |
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
App 20050263876 - Yew, Tri-Rung ; et al. | 2005-12-01 |
High density plasma chemical vapor deposition process
App 20050003671 - Liu, Chih-Chien ; et al. | 2005-01-06 |
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
App 20040084780 - Yew, Tri-Rung ; et al. | 2004-05-06 |
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
App 20030189254 - Yew, Tri-Rung ; et al. | 2003-10-09 |
Interconnect structure with air gap compatible with unlanded vias
Grant 6,492,732 - Lee , et al. December 10, 2 | 2002-12-10 |
Method for forming an interconnect structure with air gap compatible with unlanded vias
Grant 6,492,256 - Lee , et al. December 10, 2 | 2002-12-10 |
Method For Forming An Interconnect Structure With Air Gap Compatible With Unlanded Vias
App 20020163082 - Lee, Ellis ; et al. | 2002-11-07 |
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
App 20020130417 - Yew, Tri-Rung ; et al. | 2002-09-19 |
High density plasma chemical vapor deposition process
App 20020030033 - Liu, Chih-Chien ; et al. | 2002-03-14 |
Interconnect structure with gas dielectric compatible with unlanded vias
Grant 6,350,672 - Sun February 26, 2 | 2002-02-26 |
Method Of Fabricating Interconnect
App 20010027014 - SUN, SHIH-WEI | 2001-10-04 |
Interconnect structure with air gap compatible with unlanded vias
App 20010016412 - Lee, Ellis ; et al. | 2001-08-23 |
Method Of Fabricating Salicide
App 20010014533 - SUN, SHIH-WEI | 2001-08-16 |
Interconnect structure with gas dielectric compatible with unlanded vias
App 20010005625 - Sun, Shih-Wei | 2001-06-28 |
Metallization for uncovered contacts and vias
Grant 6,242,346 - Sun June 5, 2 | 2001-06-05 |
Chemical Mechanical Polishing Methods Using Low Ph Slurrymixtures
App 20010002335 - YANG, MING-SHENG ; et al. | 2001-05-31 |
Method of gap filling
Grant 6,203,863 - Liu , et al. March 20, 2 | 2001-03-20 |
Method of manufacturing multi-layer metal capacitor
Grant 6,200,629 - Sun March 13, 2 | 2001-03-13 |
Method of fabricating dual gate structure of embedded DRAM
Grant 6,153,459 - Sun November 28, 2 | 2000-11-28 |
High density plasma chemical vapor deposition process
Grant 6,117,345 - Liu , et al. September 12, 2 | 2000-09-12 |
Method of fabricating a dynamic random access memory device
Grant 6,114,200 - Yew , et al. September 5, 2 | 2000-09-05 |
Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process
Grant 6,100,205 - Liu , et al. August 8, 2 | 2000-08-08 |
Differential poly-edge oxidation for stable SRAM cells
Grant 6,025,253 - Sun February 15, 2 | 2000-02-15 |
Fabricating method of a barrier layer
Grant 6,025,264 - Yew , et al. February 15, 2 | 2000-02-15 |
Method for unlanded via etching using etch stop
Grant 6,020,258 - Yew , et al. February 1, 2 | 2000-02-01 |
Metal-oxide semiconductor field effect transistor device fabrication process
Grant 6,008,100 - Yeh , et al. December 28, 1 | 1999-12-28 |
Method of forming salicide
Grant 6,001,738 - Lin , et al. December 14, 1 | 1999-12-14 |
Process and structure for embedded DRAM
Grant 5,998,251 - Wu , et al. December 7, 1 | 1999-12-07 |
Method for increasing capacitance
Grant 5,976,931 - Yew , et al. November 2, 1 | 1999-11-02 |
Multi-step high density plasma chemical vapor deposition process
Grant 5,968,610 - Liu , et al. October 19, 1 | 1999-10-19 |
Method of fabricating a shallow-trench isolation structure in integrated circuit
Grant 5,960,299 - Yew , et al. September 28, 1 | 1999-09-28 |
Method of Making High-K Dielectrics for embedded DRAMS
Grant 5,930,618 - Sun , et al. July 27, 1 | 1999-07-27 |
Differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits
Grant 5,920,779 - Sun , et al. July 6, 1 | 1999-07-06 |
Manufacturing method for self-aligned local interconnects and contacts simultaneously
Grant 5,899,742 - Sun May 4, 1 | 1999-05-04 |
SRAM having improved soft-error immunity
Grant 5,886,375 - Sun March 23, 1 | 1999-03-23 |
Fabrication of buried channel devices with shallow junction depth
Grant 5,864,163 - Chou , et al. January 26, 1 | 1999-01-26 |
Silicon on insulator (SOI) dram cell structure and process
Grant 5,811,283 - Sun September 22, 1 | 1998-09-22 |
Dual damascene process
Grant 5,801,094 - Yew , et al. September 1, 1 | 1998-09-01 |
Method of making a self-aligned silicide component
Grant 5,780,348 - Lin , et al. July 14, 1 | 1998-07-14 |
Method for growing hemispherical grain silicon
Grant 5,753,559 - Yew , et al. May 19, 1 | 1998-05-19 |
Semiconductor device with ESD protection
Grant 5,744,841 - Gilbert , et al. April 28, 1 | 1998-04-28 |
Process for forming a semiconductor device with ESD protection
Grant 5,733,794 - Gilbert , et al. March 31, 1 | 1998-03-31 |
Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method
Grant 5,708,288 - Quigley , et al. January 13, 1 | 1998-01-13 |
Process for forming semiconductor-on-insulator device
Grant 5,670,387 - Sun September 23, 1 | 1997-09-23 |
Process for fabricating a graded-channel MOS device
Grant 5,605,855 - Chang , et al. February 25, 1 | 1997-02-25 |
Process for forming a semiconductor device having a metal-semiconductor compound
Grant 5,545,574 - Chen , et al. August 13, 1 | 1996-08-13 |
Process for forming a semiconductor region adjacent to an insulating layer
Grant 5,496,764 - Sun March 5, 1 | 1996-03-05 |
Protection device for an intergrated circuit and method of formation
Grant 5,406,111 - Sun April 11, 1 | 1995-04-11 |
Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
Grant 5,399,507 - Sun March 21, 1 | 1995-03-21 |
Method of forming dual field oxide isolation
Grant 5,369,052 - Kenkare , et al. November 29, 1 | 1994-11-29 |
Structure for shielding conductors
Grant 5,345,105 - Sun , et al. September 6, 1 | 1994-09-06 |
Process for forming a feature on a substrate without recessing the surface of the substrate
Grant 5,034,351 - Sun , et al. July 23, 1 | 1991-07-23 |
Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer
Grant 4,897,364 - Nguyen , et al. January 30, 1 | 1990-01-30 |
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