loadpatents
Patent applications and USPTO patent grants for Sumi; Yasuaki.The latest application filed is for "pll circuit".
Patent | Date |
---|---|
Phase locked loop circuit with selectable variable frequency dividers Grant 6,894,571 - Sumi , et al. May 17, 2 | 2005-05-17 |
Phase locked loop circuit having main and auxiliary frequency dividers and multiple phase comparisons Grant 6,853,222 - Sumi February 8, 2 | 2005-02-08 |
Pll circuit App 20040046612 - Sumi, Yasuaki ;   et al. | 2004-03-11 |
PLL device with plural phase comparators Grant 6,670,855 - Sumi December 30, 2 | 2003-12-30 |
PLL circuit App 20030042948 - Sumi, Yasuaki | 2003-03-06 |
PLL device and programmable frequency-division device Grant 6,522,183 - Sumi February 18, 2 | 2003-02-18 |
PLL device and programmable frequency-division device App 20020145457 - Sumi, Yasuaki | 2002-10-10 |
PLL device App 20020118053 - Sumi, Yasuaki ;   et al. | 2002-08-29 |
PLL device App 20020070812 - Sumi, Yasuaki | 2002-06-13 |
PLL circuit App 20020017956 - Sumi, Yasuaki | 2002-02-14 |
PLL device and programmable frequency-division device App 20010048329 - Sumi, Yasuaki | 2001-12-06 |
Phase-locked loop with improved trade-off between lock-up time and power dissipation Grant 6,100,767 - Sumi August 8, 2 | 2000-08-08 |
Variable Frequency Divider Grant 5,729,179 - Sumi March 17, 1 | 1998-03-17 |
Digital frequency synthesizer receiver Grant 4,081,752 - Sumi March 28, 1 | 1978-03-28 |
Multiple-band digital frequency synthesizer receiver Grant 4,048,570 - Sumi September 13, 1 | 1977-09-13 |
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