| Patent | Date |
|---|
Semiconductor devices having stressor regions and related fabrication methods
Grant 9,269,710 - Sultan , et al. February 23, 2 | 2016-02-23 |
Self-aligned silicidation for replacement gate process
Grant 8,779,529 - Sen , et al. July 15, 2 | 2014-07-15 |
Electronic device and method of biasing
Grant 8,687,417 - Li , et al. April 1, 2 | 2014-04-01 |
Semiconductor Devices Having Stressor Regions And Related Fabrication Methods
App 20130207201 - Sultan; Akif ; et al. | 2013-08-15 |
Method of fabricating multi-fingered semiconductor devices on a common substrate
Grant 8,497,179 - Sultan July 30, 2 | 2013-07-30 |
Semiconductor devices having stressor regions and related fabrication methods
Grant 8,426,278 - Sultan , et al. April 23, 2 | 2013-04-23 |
Self-aligned Silicidation For Replacement Gate Process
App 20130092957 - SEN; Indradeep ; et al. | 2013-04-18 |
Transistor with asymmetric silicon germanium source region
Grant 8,377,781 - Chen , et al. February 19, 2 | 2013-02-19 |
Self-aligned silicidation for replacement gate process
Grant 8,361,870 - Sen , et al. January 29, 2 | 2013-01-29 |
Self-aligned Silicidation For Replacement Gate Process
App 20120018816 - Sen; Indradeep ; et al. | 2012-01-26 |
Transistor With Asymmetric Silicon Germanium Source Region
App 20120003802 - Chen; Jian ; et al. | 2012-01-05 |
Semiconductor Devices Having Stressor Regions And Related Fabrication Methods
App 20110303980 - SULTAN; Akif ; et al. | 2011-12-15 |
Semiconductor device and methods for fabricating same
Grant 8,076,703 - Sultan , et al. December 13, 2 | 2011-12-13 |
Transistor with asymmetric silicon germanium source region
Grant 8,035,098 - Chen , et al. October 11, 2 | 2011-10-11 |
Method Of Fabricating Multi-fingered Semiconductor Devices On A Common Substrate
App 20110171801 - SULTAN; Akif | 2011-07-14 |
Compensating for layout dimension effects in semiconductor device modeling
Grant 7,793,240 - Sultan , et al. September 7, 2 | 2010-09-07 |
Method for fabricating a semiconductor device having an extended stress liner
Grant 7,761,838 - Shi , et al. July 20, 2 | 2010-07-20 |
Semiconductor Device And Methods For Fabricating Same
App 20100044761 - SULTAN; Akif ; et al. | 2010-02-25 |
Stress enhanced semiconductor device and methods for fabricating same
Grant 7,638,837 - Sultan , et al. December 29, 2 | 2009-12-29 |
Semiconductor device and methods for fabricating same
Grant 7,633,103 - Sultan , et al. December 15, 2 | 2009-12-15 |
Method of forming transistor devices with different threshold voltages using halo implant shadowing
Grant 7,598,161 - Zhou , et al. October 6, 2 | 2009-10-06 |
Distinguishing between dopant and line width variation components
Grant 7,582,493 - Sultan , et al. September 1, 2 | 2009-09-01 |
Electronic Device And Method Of Biasing
App 20090090969 - Li; Ruigang ; et al. | 2009-04-09 |
Stress Enhanced Semiconductor Device And Methods For Fabricating Same
App 20090078991 - SULTAN; Akif ; et al. | 2009-03-26 |
Method For Fabricating A Semiconductor Device Having An Extended Stress Liner
App 20090081837 - SHI; Zhonghai ; et al. | 2009-03-26 |
Method Of Forming Transistor Devices With Different Threshold Voltages Using Halo Implant Shadowing
App 20090081860 - ZHOU; Jingrong ; et al. | 2009-03-26 |
Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same
Grant 7,504,270 - Wu , et al. March 17, 2 | 2009-03-17 |
Semiconductor Device And Methods For Fabricating Same
App 20090057729 - SULTAN; Akif ; et al. | 2009-03-05 |
Compensating For Layout Dimension Effects In Semiconductor Device Modeling
App 20080104550 - Sultan; Akif ; et al. | 2008-05-01 |
Distinguishing Between Dopant and Line Width Variation Components
App 20080085570 - Sultan; Akif ; et al. | 2008-04-10 |
Methods Of Quantifying Variations Resulting From Manufacturing-induced Corner Rounding Of Various Features, And Structures For Testing Same
App 20070298524 - WU; DAVID D. ; et al. | 2007-12-27 |
Bi-modal halo implantation
Grant 7,176,095 - Sultan , et al. February 13, 2 | 2007-02-13 |
Methods for fabricating a stressed MOS device
App 20070026599 - Peidous; Igor ; et al. | 2007-02-01 |
Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation
Grant 6,979,635 - Sultan , et al. December 27, 2 | 2005-12-27 |
Method for improving MOS mobility
Grant 6,921,704 - Wu , et al. July 26, 2 | 2005-07-26 |
SOI MOSFET junction degradation using multiple buried amorphous layers
Grant 6,864,516 - Wei , et al. March 8, 2 | 2005-03-08 |
Maintaining LDD series resistance of MOS transistors by retarding dopant segregation
Grant 6,777,281 - Kadosh , et al. August 17, 2 | 2004-08-17 |
Formation of ultra-shallow depth source/drain extensions for MOS transistors
Grant 6,727,136 - Buller , et al. April 27, 2 | 2004-04-27 |
Hybrid silicon on insulator/bulk strained silicon technology
Grant 6,642,536 - Xiang , et al. November 4, 2 | 2003-11-04 |
SOI mosfet junction degradation using multiple buried amorphous layers
App 20030162336 - Wei, Andy ; et al. | 2003-08-28 |
Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
Grant 6,593,623 - Sultan July 15, 2 | 2003-07-15 |
Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions
Grant 6,063,682 - Sultan , et al. May 16, 2 | 2000-05-16 |
Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion
Grant 6,008,099 - Sultan , et al. December 28, 1 | 1999-12-28 |
Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
Grant 5,970,353 - Sultan October 19, 1 | 1999-10-19 |
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