Sugasawara; Emery O.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sugasawara; Emery O..The latest application filed is for "method and apparatus for avoiding dicing chip-outs in integrated circuit die".

Company Profile

0.9.1

Sugasawara; Emery O. - Pleasanton CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for avoiding dicing chip-outs in integrated circuit die Grant 7,354,790 - Rajagopalan , et al. April 8, 2	2008-04-08
Method and apparatus for avoiding dicing chip-outs in integrated circuit die App 20060160269 - Rajagopalan; Parthasarathy ; et al.	2006-07-20
Reduced voltage quiescent current test methodology for integrated circuits Grant 6,239,609 - Sugasawara , et al. May 29, 2	2001-05-29
Method of selecting and synthesizing metal interconnect wires in integrated circuits Grant 6,189,131 - Graef , et al. February 13, 2	2001-02-13
Performance monitoring circuitry for integrated circuits Grant 6,185,706 - Sugasawara February 6, 2	2001-02-06
Process monitor circuitry for integrated circuits Grant 6,124,143 - Sugasawara September 26, 2	2000-09-26
Probe points and markers for critical paths and integrated circuits Grant 6,097,884 - Sugasawara August 1, 2	2000-08-01
Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers Grant 6,061,814 - Sugasawara , et al. May 9, 2	2000-05-09
Selectable power supply lines for isolating defects in integrated circuits Grant 6,043,672 - Sugasawara March 28, 2	2000-03-28
Reticle and method of design to correct pattern for depth of focus problems Grant 5,972,541 - Sugasawara , et al. October 26, 1	1999-10-26

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