Sueki; Satoru
Patent Applications and Registrations
Patent applications and USPTO patent grants for Sueki; Satoru.The latest application filed is for "layered chip package with wiring on the side surfaces".
- Sueki; Satoru - Tokyo N/A JP
| Patent | Date |
|---|---|
| Method of manufacturing layered chip package Grant 8,513,034 - Sasaki , et al. August 20, 2 | 2013-08-20 |
| Layered chip package with wiring on the side surfaces Grant 8,324,741 - Sasaki , et al. December 4, 2 | 2012-12-04 |
| Layered chip package with heat sink Grant 8,154,116 - Sasaki , et al. April 10, 2 | 2012-04-10 |
| Layered chip package Grant 8,134,229 - Sasaki , et al. March 13, 2 | 2012-03-13 |
| Layered chip package with wiring on the side surfaces App 20110221073 - Sasaki; Yoshitaka ; et al. | 2011-09-15 |
| Method of manufacturing layered chip package App 20110201137 - Sasaki; Yoshitaka ; et al. | 2011-08-18 |
| Layered chip package with wiring on the side surfaces Grant 7,968,374 - Sasaki , et al. June 28, 2 | 2011-06-28 |
| Layered chip package and method of manufacturing same Grant 7,964,976 - Sasaki , et al. June 21, 2 | 2011-06-21 |
| Layered chip package and method of manufacturing same Grant 7,868,442 - Sasaki , et al. January 11, 2 | 2011-01-11 |
| Method of manufacturing layered chip package Grant 7,863,095 - Sasaki , et al. January 4, 2 | 2011-01-04 |
| Layered chip package App 20100327464 - Sasaki; Yoshitaka ; et al. | 2010-12-30 |
| Layered chip package and method of manufacturing same Grant 7,846,772 - Sasaki , et al. December 7, 2 | 2010-12-07 |
| Method of manufacturing layered chip package App 20100304531 - Sasaki; Yoshitaka ; et al. | 2010-12-02 |
| Layered chip package and method of manufacturing same App 20100200977 - Sasaki; Yoshitaka ; et al. | 2010-08-12 |
| Method of manufacturing layered chip package Grant 7,767,494 - Sasaki , et al. August 3, 2 | 2010-08-03 |
| Layered chip package and method of manufacturing same Grant 7,745,259 - Sasaki , et al. June 29, 2 | 2010-06-29 |
| Layered chip package with heat sink App 20100109137 - Sasaki; Yoshitaka ; et al. | 2010-05-06 |
| Layered chip package and method of manufacturing same App 20100044879 - Sasaki; Yoshitaka ; et al. | 2010-02-25 |
| Layered chip package and method of manufacturing same App 20090321957 - Sasaki; Yoshitaka ; et al. | 2009-12-31 |
| Layered chip package and method of manufacturing same App 20090321956 - Sasaki; Yoshitaka ; et al. | 2009-12-31 |
| Method of manufacturing layered chip package App 20090325345 - Sasaki; Yoshitaka ; et al. | 2009-12-31 |
| Layered chip package and method of manufacturing same App 20090315189 - Sasaki; Yoshitaka ; et al. | 2009-12-24 |
| Layered chip package that implements memory device Grant 7,557,439 - Sasaki , et al. July 7, 2 | 2009-07-07 |
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