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Transmission Gate Manufacturing Method
App 20220188501 - CHIEN; Shao-Lun ; et al. | 2022-06-16 |
Reduced Area Standard Cell Abutment Configurations
App 20220114322 - LU; Chi-Yu ; et al. | 2022-04-14 |
Transmission gate structure and method
Grant 11,295,055 - Chien , et al. April 5, 2 | 2022-04-05 |
Integrated circuit layout and method of configuring the same
Grant 11,239,228 - Lin , et al. February 1, 2 | 2022-02-01 |
Reduced area standard cell abutment configurations
Grant 11,216,608 - Lu , et al. January 4, 2 | 2022-01-04 |
Semiconductor Device And Layout Design Thereof
App 20210343636 - Lin; Chung-Te ; et al. | 2021-11-04 |
Integrated Circuit Having Fins Crossing Cell Boundary
App 20210313319 - SUE; Pin-Dai ; et al. | 2021-10-07 |
Method For Manufacturing A Cell Having Pins And Semiconductor Device Based On Same
App 20210294957 - SUE; Pin-Dai ; et al. | 2021-09-23 |
Semiconductor Device
App 20210273093 - Lu; Ze-Sian ; et al. | 2021-09-02 |
Semiconductor device and layout design thereof
Grant 11,088,067 - Lin , et al. August 10, 2 | 2021-08-10 |
Power Switch Circuit, Ic Structure Of Power Switch Circuit, And Method Of Forming Ic Structure
App 20210218398 - HUNG; TZUNG-YO ; et al. | 2021-07-15 |
Method for generating layout diagram including cell having pin patterns and semiconductor device based on same
Grant 11,030,372 - Sue , et al. June 8, 2 | 2021-06-08 |
Double Rule Integrated Circuit Layouts For A Dual Transmission Gate
App 20210098453 - PENG; Shih-Wei ; et al. | 2021-04-01 |
Isolation Circuit Between Power Domains
App 20210089700 - LU; Chi-Yu ; et al. | 2021-03-25 |
Transmission Gate Structure And Method
App 20210089702 - CHIEN; Shao-Lun ; et al. | 2021-03-25 |
Semiconductor Device Having Fin Structure
App 20210091066 - CHEN; SHUN-LI ; et al. | 2021-03-25 |
Integrated circuit and method of fabricating the same
Grant 10,950,594 - Lin , et al. March 16, 2 | 2021-03-16 |
Semiconductor Device
App 20200411516 - SUE; Pin-Dai ; et al. | 2020-12-31 |
Tie Off Device
App 20200402979 - Chien; Shao-Lun ; et al. | 2020-12-24 |
Semiconductor device having fin structure
Grant 10,867,986 - Chen , et al. December 15, 2 | 2020-12-15 |
Double rule integrated circuit layouts for a dual transmission gate
Grant 10,868,008 - Peng , et al. December 15, 2 | 2020-12-15 |
Transmission gate structure, layout, methods, and system
Grant 10,867,113 - Chien , et al. December 15, 2 | 2020-12-15 |
Isolation circuit between power domains
Grant 10,867,104 - Lu , et al. December 15, 2 | 2020-12-15 |
Power strap structure for high performance and low current density
Grant 10,861,790 - Chen , et al. December 8, 2 | 2020-12-08 |
Integrated Circuit Layout and Method of Configuring the Same
App 20200335489 - Lin; Chung-Te ; et al. | 2020-10-22 |
Semiconductor Device and Layout Design Thereof
App 20200328148 - Lin; Chung-Te ; et al. | 2020-10-15 |
Semiconductor device and layout design thereof
Grant 10,727,177 - Lin , et al. | 2020-07-28 |
Integrated circuit layout and method of configuring the same
Grant 10,707,199 - Lin , et al. | 2020-07-07 |
Double Rule Integrated Circuit Layouts For A Dual Transmission Gate
App 20200135732 - PENG; Shih-Wei ; et al. | 2020-04-30 |
Reduced Area Standard Cell Abutment Configurations
App 20200134126 - LU; Chi-Yu ; et al. | 2020-04-30 |
Method For Generating Layout Diagram Including Cell Having Pin Patterns And Semiconductor Device Based On Same
App 20200134124 - SUE; Pin-Dai ; et al. | 2020-04-30 |
Transmission Gate Structure, Layout, Methods, And System
App 20200082052 - CHIEN; Shao-Lun ; et al. | 2020-03-12 |
Isolation Circuit Between Power Domains
App 20200074039 - LU; Chi-Yu ; et al. | 2020-03-05 |
Double Rule Integrated Circuit Layouts For A Dual Transmission Gate
App 20200006338 - PENG; Shih-Wei ; et al. | 2020-01-02 |
Double rule integrated circuit layouts for a dual transmission gate
Grant 10,522,542 - Peng , et al. Dec | 2019-12-31 |
Method For Generating Layout Diagram Including Wiring Arrangement
App 20190286784 - CHANG; Fong-Yuan ; et al. | 2019-09-19 |
Integrated Circuit and Method of Fabricating the Same
App 20190279975 - Lin; Chung-Te ; et al. | 2019-09-12 |
Integrated Circuit Layout and Method of Configuring the Same
App 20190252367 - Lin; Chung-Te ; et al. | 2019-08-15 |
Semiconductor Device Having Fin Structure
App 20190189609 - CHEN; SHUN-LI ; et al. | 2019-06-20 |
Integrated circuit and method of fabricating the same
Grant 10,325,900 - Lin , et al. | 2019-06-18 |
Semiconductor device layout
Grant 10,277,227 - Sue , et al. | 2019-04-30 |
Power Strap Structure For High Performance And Low Current Density
App 20190122987 - Chen; Chih-Liang ; et al. | 2019-04-25 |
Integrated circuit layout and method of configuring the same
Grant 10,269,784 - Lin , et al. | 2019-04-23 |
Semiconductor Device and Layout Design Thereof
App 20190067185 - Lin; Chung-Te ; et al. | 2019-02-28 |
Power strap structure for high performance and low current density
Grant 10,170,422 - Chen , et al. J | 2019-01-01 |
Integrated circuit and method of fabricating the same
Grant 10,163,880 - Lin , et al. Dec | 2018-12-25 |
Semiconductor device and layout design thereof
Grant 10,141,256 - Lin , et al. Nov | 2018-11-27 |
Integrated Circuit and Method of Fabricating the Same
App 20180337167 - Lin; Chung-Te ; et al. | 2018-11-22 |
Power Strap Structure For High Performance And Low Current Density
App 20180174967 - Chen; Chih-Liang ; et al. | 2018-06-21 |
Power strap structure for high performance and low current density
Grant 9,911,697 - Chen , et al. March 6, 2 | 2018-03-06 |
Integrated Circuit Layout And Method Of Configuring The Same
App 20180006009 - LIN; Chung-Te ; et al. | 2018-01-04 |
Semiconductor Device Layout
App 20170346490 - Sue; Pin-Dai ; et al. | 2017-11-30 |
Integrated Circuit And Method Of Fabricating The Same
App 20170323877 - LIN; Chung-Te ; et al. | 2017-11-09 |
Power Strap Structure For High Performance And Low Current Density
App 20170317027 - Chen; Chih-Liang ; et al. | 2017-11-02 |
Semiconductor Device And Layout Design Thereof
App 20170309562 - LIN; Chung-Te ; et al. | 2017-10-26 |
Cell boundaries for self aligned multiple patterning abutments
Grant 9,563,731 - Hsu , et al. February 7, 2 | 2017-02-07 |
Integrated circuit with multiple cells having different heights
Grant 9,478,609 - Chiang , et al. October 25, 2 | 2016-10-25 |
Adaptive fin design for FinFETs
Grant 9,478,540 - Ou , et al. October 25, 2 | 2016-10-25 |
Integrated Circuit With Multiple Cells Having Different Heights
App 20160013271 - CHIANG; Ting-Wei ; et al. | 2016-01-14 |
Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits
Grant 9,202,696 - Yang , et al. December 1, 2 | 2015-12-01 |
Method For Designing Antenna Cell That Prevents Plasma Induced Gate Dielectric Damage In Semiconductor Integrated Circuits
App 20150031194 - YANG; Jen-Hang ; et al. | 2015-01-29 |
Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits
Grant 8,872,269 - Yang , et al. October 28, 2 | 2014-10-28 |
Cell Boundaries For Self Aligned Multiple Patterning Abutments
App 20140282289 - Hsu; Chin-Hsiung ; et al. | 2014-09-18 |
Self-aligned multiple patterning layout design
Grant 8,799,834 - Chen , et al. August 5, 2 | 2014-08-05 |
Self-aligned Multiple Patterning Layout Design
App 20140215421 - Chen; Huang-Yu ; et al. | 2014-07-31 |
Adaptive Fin Design for FinFETs
App 20140203378 - Ou; Tsong-Hua ; et al. | 2014-07-24 |
Adaptive fin design for FinFETs
Grant 8,728,892 - Ou , et al. May 20, 2 | 2014-05-20 |
Integrated circuit layouts with power rails under bottom metal layer
Grant 8,507,957 - Hou , et al. August 13, 2 | 2013-08-13 |
Antenna Cell Design To Prevent Plasma Induced Gate Dielectric Damage In Semiconductor Integrated Circuits
App 20130146981 - YANG; Jen-Hang ; et al. | 2013-06-13 |
Adaptive Fin Design for FinFETs
App 20120280331 - Ou; Tsong-Hua ; et al. | 2012-11-08 |
Integrated Circuit Layouts with Power Rails under Bottom Metal Layer
App 20120280287 - Hou; Yung-Chin ; et al. | 2012-11-08 |
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