loadpatents
name:-0.0097019672393799
name:-0.010833024978638
name:-0.0018401145935059
SUBBANNAVAR; Badarish Mohan Patent Filings

SUBBANNAVAR; Badarish Mohan

Patent Applications and Registrations

Patent applications and USPTO patent grants for SUBBANNAVAR; Badarish Mohan.The latest application filed is for "reduced area, reduced power flip-flop".

Company Profile
1.8.9
  • SUBBANNAVAR; Badarish Mohan - Bengaluru IN
  • Subbannavar; Badarish Mohan - Bangalore IN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Reduced Area, Reduced Power Flip-flop
App 20210265985 - SUBBANNAVAR; Badarish Mohan ;   et al.
2021-08-26
Reduced area, reduced power flip-flop
Grant 11,043,937 - Subbannavar , et al. June 22, 2
2021-06-22
Reduced Area, Reduced Power Flip-flop
App 20210184659 - SUBBANNAVAR; Badarish Mohan ;   et al.
2021-06-17
Ultra-Low Power Static State Flip Flop
App 20190319612 - Nandi; Suvam ;   et al.
2019-10-17
Ultra-low power static state flip flop
Grant 10,382,020 - Nandi , et al. A
2019-08-13
Ultra-Low Power Static State Flip Flop
App 20180331675 - Nandi; Suvam ;   et al.
2018-11-15
Ultra-low power static state flip flop
Grant 10,056,882 - Nandi , et al. August 21, 2
2018-08-21
Ultra-low Power Static State Flip Flop
App 20170194943 - NANDI; Suvam ;   et al.
2017-07-06
Low area full adder with shared transistors
Grant 9,471,278 - Nandi , et al. October 18, 2
2016-10-18
Low area flip-flop with a shared inverter
Grant 9,425,771 - Nandi , et al. August 23, 2
2016-08-23
Flip-flops with low clock power
Grant 9,350,327 - Nandi , et al. May 24, 2
2016-05-24
Low Area Flip-flop With A Shared Inverter
App 20160094203 - Nandi; Suvam ;   et al.
2016-03-31
Flip-flops With Low Clock Power
App 20160094204 - Nandi; Suvam ;   et al.
2016-03-31
Low Area Full Adder With Shared Transistors
App 20160092170 - Nandi; Suvam ;   et al.
2016-03-31
Integrated clock gating cell using a low area and a low power latch
Grant 9,246,489 - Nandi , et al. January 26, 2
2016-01-26
Multi-bit Interlaced Latch
App 20120025885 - LAVERY; Kevin P. ;   et al.
2012-02-02
Functional-input sequential circuit
Grant 7,825,689 - Vasishta , et al. November 2, 2
2010-11-02

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed