Subbanna; Seshadri

Patent Applications and Registrations

Patent applications and USPTO patent grants for Subbanna; Seshadri.The latest application filed is for "selective epitaxial growth by incubation time engineering".

Company Profile

0.27.13

Subbanna; Seshadri - Brewster NY
Subbanna; Seshadri - Hopewell Junction NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated microfluidics system Grant 9,643,181 - Chang , et al. May 9, 2	2017-05-09
Selective Epitaxial Growth By Incubation Time Engineering App 20120295417 - Adam; Thomas N. ; et al.	2012-11-22
Multi-level RF passive device Grant 7,053,460 - Volant , et al. May 30, 2	2006-05-30
Method for BEOL resistor tolerance improvement using anodic oxidation Grant 6,933,186 - Cotte , et al. August 23, 2	2005-08-23
Bipolar device having shallow junction raised extrinsic base and method for making the same Grant 6,927,476 - Freeman , et al. August 9, 2	2005-08-09
Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling Grant 6,858,532 - Natzle , et al. February 22, 2	2005-02-22
Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers Grant 6,800,921 - Coolbaugh , et al. October 5, 2	2004-10-05
MEMS encapsulated structure and method of making same Grant 6,800,503 - Kocis , et al. October 5, 2	2004-10-05
Method of fabricating micro-electromechanical switches on CMOS compatible substrates Grant 6,798,029 - Volant , et al. September 28, 2	2004-09-28
BiCMOS integration scheme with raised extrinsic base Grant 6,780,695 - Chen , et al. August 24, 2	2004-08-24
Nitride pedestal for raised extrinsic base HBT process Grant 6,777,302 - Chen , et al. August 17, 2	2004-08-17
Method Of Fabricating Micro-electromechanical Switches On Cmos Compatible Substrates App 20040126921 - Volant, Richard P. ; et al.	2004-07-01
Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling App 20040110354 - Natzle, Wesley C. ; et al.	2004-06-10
MEMS encapsulated structure and method of making same App 20040097003 - Kocis, Joseph T. ; et al.	2004-05-20
Apparatus and method for forming uniformly thick anodized films on large substrates App 20040077140 - Andricacos, Panayotis C. ; et al.	2004-04-22
Micro-electromechanical varactor with enhanced tuning range Grant 6,696,343 - Chinthakindi , et al. February 24, 2	2004-02-24
Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers Grant 6,670,228 - Coolbaugh , et al. December 30, 2	2003-12-30
Micro-electromechanical varactor with enhanced tuning range Grant 6,661,069 - Chinthakindi , et al. December 9, 2	2003-12-09
Method of fabricating micro-electromechanical switches on CMOS compatible substrates Grant 6,635,506 - Volant , et al. October 21, 2	2003-10-21
Method Of Fabricating Micro-electromechanical Switches On Cmos Compatible Substrates App 20030148550 - Volant, Richard P. ; et al.	2003-08-07
Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers App 20030141534 - Coolbaugh, Douglas Duane ; et al.	2003-07-31
Multi-level RF passive device App 20030116850 - Volant, Richard P. ; et al.	2003-06-26
Method for BEOL resistor tolerance improvement using anodic oxidation App 20030059992 - Cotte, John M. ; et al.	2003-03-27
Bipolar device having shallow junction raised extrinsic base and method for making the same App 20030057458 - Freeman, Gregory G. ; et al.	2003-03-27
Non-self-aligned SiGe heterojunction bipolar transistor App 20020197807 - Jagannathan, Basanth ; et al.	2002-12-26
Method for epitaxial bipolar BiCMOS Grant 6,448,124 - Coolbaugh , et al. September 10, 2	2002-09-10
Method For Epitaxial Bipolar Bicmos App 20020076874 - COOLBAUGH, DOUGLAS D. ; et al.	2002-06-20
Lateral Polysilicon Pin Diode And Method For So Fabricating App 20020070388 - Greenberg, David R. ; et al.	2002-06-13
Selective plating process Grant 6,368,484 - Volant , et al. April 9, 2	2002-04-09
Pattern-sensitive electrolytic metal plating Grant 6,344,125 - Locke , et al. February 5, 2	2002-02-05
Device formed by selective deposition of refractory metal of less than 300 Angstroms of thickness Grant 6,049,131 - Brodsky , et al. April 11, 2	2000-04-11
Method for selective deposition of refractory metal and device formed thereby Grant 5,807,788 - Brodsky , et al. September 15, 1	1998-09-15
Method of making a CMOS structure with FETS having isolated wells with merged depletions Grant 5,789,286 - Subbanna August 4, 1	1998-08-04
One dimensional silicon quantum wire devices and the method of manufacture thereof Grant 5,612,255 - Chapple-Sokol , et al. March 18, 1	1997-03-18
Antifuse element with electrical or optical programming Grant 5,485,032 - Schepis , et al. January 16, 1	1996-01-16
Method of making semiconductor quantum dot light emitting/detecting devices Grant 5,354,707 - Chapple-Sokol , et al. October 11, 1	1994-10-11
Method of fabricating an ultra-short channel field effect transistor Grant 5,338,698 - Subbanna August 16, 1	1994-08-16
Semiconductor quantum dot light emitting/detecting devices Grant 5,293,050 - Chapple-Sokol , et al. March 8, 1	1994-03-08
Modified silicon CMOS process having selectively deposited Si/SiGe FETS Grant 5,268,324 - Aitken , et al. December 7, 1	1993-12-07
Low temperature emitter process for high performance bipolar devices Grant 5,266,504 - Blouse , et al. November 30, 1	1993-11-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.