Su; Chauchin
Patent Applications and Registrations
Patent applications and USPTO patent grants for Su; Chauchin.The latest application filed is for "method and system for layout parasitic estimation".
- Su; Chauchin - Taipei N/A TW
- SU; Chauchin - Taipei City TW
| Patent | Date |
|---|---|
| Method and system for layout parasitic estimation Grant 8,806,414 - Huang , et al. August 12, 2 | 2014-08-12 |
| On-the-fly device characterization from layouts of circuits Grant 8,726,207 - Jiang , et al. May 13, 2 | 2014-05-13 |
| Method And System For Layout Parasitic Estimation App 20130326447 - HUANG; Mu-Jen ; et al. | 2013-12-05 |
| On-the-Fly Device Characterization from Layouts of Circuits App 20120304146 - Jiang; Yu-Sian ; et al. | 2012-11-29 |
| Buffer circuit Grant 7,764,086 - Lu , et al. July 27, 2 | 2010-07-27 |
| Buffer Circuit App 20080150583 - LU; Hung Wen ; et al. | 2008-06-26 |
| IEEE Std. 1149.4 compatible analog BIST methodology Grant 7,228,479 - Su , et al. June 5, 2 | 2007-06-05 |
| IEEE Std. 1149.4 compatible analog BIST methodology App 20060059395 - Su; Chauchin ; et al. | 2006-03-16 |
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