loadpatents
name:-0.04944896697998
name:-0.037797927856445
name:-0.00052404403686523
Su; Chao-Yuan Patent Filings

Su; Chao-Yuan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Su; Chao-Yuan.The latest application filed is for "lateral diffused metal oxide semiconductor".

Company Profile
0.35.44
  • Su; Chao-Yuan - Hsin-Chu TW
  • Su; Chao-Yuan - Tainan City TW
  • Su; Chao-Yuan - Koahsiung N/A TW
  • Su; Chao-Yuan - Kaohsiung N/A TW
  • Su; Chao-Yuan - Hsinchu TW
  • Su; Chao-Yuan - Hsinchu City TW
  • Su; Chao-Yuan - Hsin-Chu County TW
  • Su; Chao-Yuan - Baoshan Township Hsinchu County TW
  • Su; Chao-Yuan - Koahsiung City TW
  • Su; Chao-Yuan - Koaksiung TW
  • Su; Chao-Yuan - Kaohsiung City TW
  • Su; Chao-Yuan - Koahsiang TW
  • Su, Chao-Yuan - Koahsiang City TW
  • Su; Chao-Yuan - Koashiung TW
  • Su, Chao-Yuan - Hsin-chu City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Exclusion zone for stress-sensitive circuit design
Grant 9,691,749 - Su , et al. June 27, 2
2017-06-27
Lateral Diffused Metal Oxide Semiconductor
App 20150115362 - Su; Chao-Yuan ;   et al.
2015-04-30
Lateral Diffused Metal Oxide Semiconductor
App 20150115361 - Su; Chao-Yuan ;   et al.
2015-04-30
Exclusion Zone for Stress-Sensitive Circuit Design
App 20140346644 - Su; Chao-Yuan ;   et al.
2014-11-27
Exclusion zone for stress-sensitive circuit design
Grant 8,829,653 - Su , et al. September 9, 2
2014-09-09
Exclusion Zone for Stress-Sensitive Circuit Design
App 20140087492 - Su; Chao-Yuan ;   et al.
2014-03-27
Method for packaging semiconductor dies having through-silicon vias
Grant 8,629,563 - Su January 14, 2
2014-01-14
Exclusion zone for stress-sensitive circuit design
Grant 8,624,346 - Su , et al. January 7, 2
2014-01-07
Method to improve bump reliability for flip chip device
Grant 8,497,584 - Chen , et al. July 30, 2
2013-07-30
Method for Packaging Semiconductor Dies Having Through-Silicon Vias
App 20120146238 - Su; Chao-Yuan
2012-06-14
Method for packaging semiconductor dies having through-silicon vias
Grant 8,124,458 - Su February 28, 2
2012-02-28
Fluxless bumping process
Grant 7,906,425 - Su , et al. March 15, 2
2011-03-15
Nail-shaped pillar for wafer-level chip-scale packaging
Grant 7,892,962 - Su February 22, 2
2011-02-22
Method for Packaging Semiconductor Dies Having Through-Silicon Vias
App 20110014749 - Su; Chao-Yuan
2011-01-20
Method for packaging semiconductor dies having through-silicon vias
Grant 7,825,517 - Su November 2, 2
2010-11-02
High-voltage MOS transistor device
Grant 7,719,076 - Shu , et al. May 18, 2
2010-05-18
High-voltage MOS transistor device
Grant 7,709,908 - Su , et al. May 4, 2
2010-05-04
Method For Forming Deep Well Region Of High Voltage Device
App 20090111252 - Huang; Chih-Jen ;   et al.
2009-04-30
Nail-Shaped Pillar for Wafer-Level Chip-Scale Packaging
App 20090057896 - Su; Chao-Yuan
2009-03-05
High-voltage Mos Transistor Device
App 20090039425 - Shu; Shih-Ming ;   et al.
2009-02-12
High-voltage Mos Transistor Device
App 20090039424 - Su; Chao-Yuan ;   et al.
2009-02-12
Method for Packaging Semiconductor Dies Having Through-Silicon Vias
App 20090020865 - Su; Chao-Yuan
2009-01-22
Application of impressed-current cathodic protection to prevent metal corrosion and oxidation
Grant 7,468,321 - Ching , et al. December 23, 2
2008-12-23
Novel substrate design for semiconductor device
App 20080246147 - Su; Chao-Yuan ;   et al.
2008-10-09
Stress buffer layer for packaging process
App 20080203566 - Su; Chao-Yuan
2008-08-28
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
Grant 7,294,937 - Su , et al. November 13, 2
2007-11-13
Application of impressed-current cathodic protection to prevent metal corrosion and oxidation
Grant 7,276,454 - Ching , et al. October 2, 2
2007-10-02
Underfilling efficiency by modifying the substrate design of flip chips
Grant 7,256,071 - Lee , et al. August 14, 2
2007-08-14
Exclusion zone for stress-sensitive circuit design
App 20070090547 - Su; Chao-Yuan ;   et al.
2007-04-26
Packages, anisotropic conductive films, and conductive particles utilized therein
App 20070063347 - Su; Chao-Yuan
2007-03-22
Fluxless bumping process
App 20070028445 - Su; Chao-Yuan ;   et al.
2007-02-08
Semiconductor bond pad structures and methods of manufacturing thereof
Grant 7,157,734 - Tsao , et al. January 2, 2
2007-01-02
Encapsulation method for SBGA
Grant 7,154,185 - Lee , et al. December 26, 2
2006-12-26
Semiconductor Bond Pad Structures And Methods Of Manufacturing Thereof
App 20060267008 - Tsao; Pei-Haw ;   et al.
2006-11-30
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
App 20060261490 - Su; Chao-Yuan ;   et al.
2006-11-23
Fluxless bumping process
Grant 7,134,199 - Su , et al. November 14, 2
2006-11-14
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
Grant 7,126,225 - Su , et al. October 24, 2
2006-10-24
Non-cavity semiconductor packages
App 20060231960 - Su; Chao-Yuan ;   et al.
2006-10-19
Underfilling Efficiency By Modifying The Substrate Design Of Flip Chips
App 20060202351 - Lee; Hsin-Hui ;   et al.
2006-09-14
Substrate design to improve chip package reliability
Grant 7,105,920 - Su , et al. September 12, 2
2006-09-12
Application Of Impressed-current Cathodic Protection To Prevent Metal Corrosion And Oxidation
App 20060194407 - Ching; Kai-Ming ;   et al.
2006-08-31
Microelectronics package assembly tool and method of manufacture therewith
Grant 7,098,082 - Su , et al. August 29, 2
2006-08-29
Novel method for copper wafer wire bonding
App 20060170114 - Su; Chao-Yuan ;   et al.
2006-08-03
Underfilling efficiency by modifying the substrate design of flip chips
Grant 7,075,016 - Lee , et al. July 11, 2
2006-07-11
Test pad and probe card for wafer acceptance testing and other applications
App 20060109014 - Chao; Te-Tsung ;   et al.
2006-05-25
Substrate design to improve chip package reliability
App 20060103006 - Su; Chao-Yuan ;   et al.
2006-05-18
Fine pitch bonding pad layout and method of manufacturing same
App 20060091535 - Tsao; Pei-Haw ;   et al.
2006-05-04
Semiconductor Package Substrate For Flip Chip Packaging
App 20060076681 - Tsao; Pei-Haw ;   et al.
2006-04-13
Three dimensional package type stacking for thinner package application
App 20060073635 - Su; Chao-Yuan ;   et al.
2006-04-06
Three dimensional package and packaging method for integrated circuits
App 20060065958 - Tsao; Pei-Haw ;   et al.
2006-03-30
Stacked packaging methods and structures
App 20060043556 - Su; Chao-Yuan ;   et al.
2006-03-02
Method of forming a solder ball using a thermally stable resinous protective layer
Grant 6,974,659 - Su , et al. December 13, 2
2005-12-13
Microelectronics package assembly tool and method of manufacture therewith
App 20050227409 - Su, Chao-Yuan ;   et al.
2005-10-13
Underfilling efficiency by modifying the substrate design of flip chips
App 20050178581 - Lee, Hsin-Hui ;   et al.
2005-08-18
Novel encapsulation method for SBGA
App 20050112795 - Lee, Hsin-Hui ;   et al.
2005-05-26
Flip chip assembly process and substrate used therewith
App 20040232560 - Su, Chao-Yuan
2004-11-25
Process for bonding solder bumps to a substrate
Grant 6,821,813 - Su November 23, 2
2004-11-23
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
App 20040207078 - Su, Chao-Yuan ;   et al.
2004-10-21
Fluxless bumping process using ions
Grant 6,805,279 - Lee , et al. October 19, 2
2004-10-19
Stencil design for solder paste printing
Grant 6,802,250 - Su , et al. October 12, 2
2004-10-12
Novel method to improve bump reliability for flip chip device
App 20040180296 - Chen, Yen-Ming ;   et al.
2004-09-16
Flip chip process of flux-less no-flow underfill
Grant 6,770,510 - Su August 3, 2
2004-08-03
Method for improving bump reliability for flip chip devices
Grant 6,756,294 - Chen , et al. June 29, 2
2004-06-29
Process for bonding solder bumps to a substrate
App 20040121576 - Su, Chao-Yuan
2004-06-24
Method of making a wafer level chip scale package
Grant 6,743,660 - Lee , et al. June 1, 2
2004-06-01
Application of impressed-current cathodic protection to prevent metal corrosion and oxidation
App 20040087175 - Ching, Kai-Ming ;   et al.
2004-05-06
DFR laminating and film removing system
Grant 6,715,524 - Chen , et al. April 6, 2
2004-04-06
Fluxless bumping process using ions
App 20040000580 - Lee, Hsin-Hui ;   et al.
2004-01-01
Fluxless bumping process
App 20030229986 - Su, Chao-Yuan ;   et al.
2003-12-18
DFR laminating and film removing system
App 20030226638 - Chen, Li-Chih ;   et al.
2003-12-11
Stencil design for solder paste printing
App 20030213384 - Su, Chao-Yuan ;   et al.
2003-11-20
Method of measuring photoresist and bump misalignment
Grant 6,636,313 - Chen , et al. October 21, 2
2003-10-21
Method to improve reliability for flip-chip device for limiting pad design
Grant 6,602,775 - Chen , et al. August 5, 2
2003-08-05
Method of measuring photoresist and bump misalignment
App 20030133115 - Chen, Yen-Ming ;   et al.
2003-07-17
Method of forming a solder ball using a thermally stable resinous protective layer
App 20030134233 - Su, Chao-Yuan ;   et al.
2003-07-17
Method of making a wafer level chip scale package
App 20030134496 - Lee, Hsin-Hui ;   et al.
2003-07-17

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