loadpatents
name:-0.038420915603638
name:-0.037654161453247
name:-0.017149925231934
Strane; Jay W. Patent Filings

Strane; Jay W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Strane; Jay W..The latest application filed is for "dual width finned semiconductor structure".

Company Profile
13.30.28
  • Strane; Jay W. - Warwick NY
  • Strane; Jay W. - Hopewell Junction NY
  • Strane; Jay W. - Wappingers Falls NY
  • Strane; Jay W. - Chester NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dual width finned semiconductor structure
Grant 11,189,532 - Song , et al. November 30, 2
2021-11-30
Semiconductor fins with dielectric isolation at fin bottom
Grant 11,043,429 - Xu , et al. June 22, 2
2021-06-22
Controlling active fin height of FinFET device
Grant 10,892,193 - Song , et al. January 12, 2
2021-01-12
Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
Grant 10,770,361 - Song , et al. Sep
2020-09-08
Dual Width Finned Semiconductor Structure
App 20200194314 - Song; Yi ;   et al.
2020-06-18
Controlling Active Fin Height Of Finfet Device Using Etch Protection Layer To Prevent Recess Of Isolation Layer During Gate Oxid
App 20200176332 - Song; Yi ;   et al.
2020-06-04
Dual width finned semiconductor structure
Grant 10,672,668 - Song , et al.
2020-06-02
Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
Grant 10,665,514 - Song , et al.
2020-05-26
Semiconductor Fins With Dielectric Isolation At Fin Bottom
App 20200152520 - Xu; Peng ;   et al.
2020-05-14
Semiconductor fins with dielectric isolation at fin bottom
Grant 10,636,709 - Xu , et al.
2020-04-28
Protection of low temperature isolation fill
Grant 10,586,700 - Belyansky , et al.
2020-03-10
Controlling Active Fin Height Of Finfet Device Using Etch Protection Layer To Prevent Recess Of Isolation Layer During Gate Oxid
App 20200027796 - Song; Yi ;   et al.
2020-01-23
Protection of low temperature isolation fill
Grant 10,535,550 - Belyansky , et al. Ja
2020-01-14
Controlling Active Fin Height Of Finfet Device Using Etch Protection Layer To Prevent Recess Of Isolation Layer During Gate Oxid
App 20190385916 - Song; Yi ;   et al.
2019-12-19
Dual Width Finned Semiconductor Structure
App 20190371678 - Song; Yi ;   et al.
2019-12-05
Semiconductor Fins With Dielectric Isolation At Fin Bottom
App 20190311955 - Xu; Peng ;   et al.
2019-10-10
Protection Of Low Temperature Isolation Fill
App 20190067078 - Belyansky; Michael P. ;   et al.
2019-02-28
Protection Of Low Temperature Isolation Fill
App 20190067079 - Belyansky; Michael P. ;   et al.
2019-02-28
Uniform dielectric recess depth during fin reveal
Grant 9,984,935 - Briggs , et al. May 29, 2
2018-05-29
Uniform dielectric recess depth during fin reveal
Grant 9,984,916 - Briggs , et al. May 29, 2
2018-05-29
Uniform dielectric recess depth during fin reveal
Grant 9,941,134 - Briggs , et al. April 10, 2
2018-04-10
Uniform Dielectric Recess Depth During Fin Reveal
App 20170236717 - Briggs; Benjamin D. ;   et al.
2017-08-17
Uniform Dielectric Recess Depth During Fin Reveal
App 20170236756 - Briggs; Benjamin D. ;   et al.
2017-08-17
Uniform dielectric recess depth during fin reveal
Grant 9,666,474 - Briggs , et al. May 30, 2
2017-05-30
Uniform Dielectric Recess Depth During Fin Reveal
App 20170125286 - Briggs; Benjamin D. ;   et al.
2017-05-04
Uniform Dielectric Recess Depth During Fin Reveal
App 20170125302 - Briggs; Benjamin D. ;   et al.
2017-05-04
Semiconductor structures having improved contact resistance
Grant 8,685,809 - Doris , et al. April 1, 2
2014-04-01
Replacement gate MOSFET with self-aligned diffusion contact
Grant 8,421,077 - Jain , et al. April 16, 2
2013-04-16
Semiconductor structures having improved contact resistance
Grant 8,299,455 - Doris , et al. October 30, 2
2012-10-30
Semiconductor Structures Having Improved Contact Resistance
App 20120208332 - Doris; Bruce B. ;   et al.
2012-08-16
Semiconductor Structures Having Improved Contact Resistance
App 20120132966 - Doris; Bruce B. ;   et al.
2012-05-31
Pedestal guard ring having continuous M1 metal barrier connected to crack stop
Grant 8,188,574 - Angyal , et al. May 29, 2
2012-05-29
Method and process for forming a self-aligned silicide contact
Grant 8,101,518 - Cabral, Jr. , et al. January 24, 2
2012-01-24
Replacement Gate Mosfet With Self-aligned Diffusion Contact
App 20110298017 - Jain; Sameer H. ;   et al.
2011-12-08
Method for forming self-aligned metal silicide contacts
Grant 8,039,382 - Fang , et al. October 18, 2
2011-10-18
Methods for forming high performance gates and structures thereof
Grant 7,790,553 - Zhu , et al. September 7, 2
2010-09-07
Pedestal Guard Ring Having Continuous M1 Metal Barrier Connected To Crack Stop
App 20100200958 - Angyal; Matthew S. ;   et al.
2010-08-12
Methods For Forming High Performance Gates And Structures Thereof
App 20100006926 - ZHU; HUILONG ;   et al.
2010-01-14
Method For Forming Self-aligned Metal Silicide Contacts
App 20090309228 - Fang; Sunfei ;   et al.
2009-12-17
Method for forming self-aligned metal silicide contacts
Grant 7,618,891 - Fang , et al. November 17, 2
2009-11-17
Method and process for forming a self-aligned silicide contact
Grant 7,544,610 - Cabral, Jr. , et al. June 9, 2
2009-06-09
Method And Process For Forming A Self-aligned Silicide Contact
App 20080274611 - Cabral; Cyril ;   et al.
2008-11-06
STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE
App 20080173942 - Zhu; Huilong ;   et al.
2008-07-24
Method for forming self-aligned metal silicide contacts
App 20070254479 - Fang; Sunfei ;   et al.
2007-11-01
Improved Thermal Budget Using Nickel Based Silicides For Enhanced Semiconductor Device Performance
App 20070249149 - Deshpande; Sadanand V. ;   et al.
2007-10-25
Air gap interconnect structure and method of manufacture
Grant 7,041,571 - Strane May 9, 2
2006-05-09
Trench formation in semiconductor integrated circuits (ICs)
Grant 6,989,317 - Radens , et al. January 24, 2
2006-01-24
Low Cu percentages for reducing shorts in AlCu lines
Grant 6,960,306 - Iggulden , et al. November 1, 2
2005-11-01
Air Gap Interconnect Structure And Method Of Manufacture
App 20050191862 - Strane, Jay W.
2005-09-01
Silicide Resistor In Beol Layer Of Semiconductor Device And Method
App 20050130383 - Divakaruni, Ramachandra ;   et al.
2005-06-16
Etching openings of different depths using a single mask layer method and structure
Grant 6,887,785 - Dobuzinsky , et al. May 3, 2
2005-05-03
Self-aligned borderless contacts
Grant 6,809,027 - Strane , et al. October 26, 2
2004-10-26
Method of making self-aligned borderless contacts
Grant 6,806,177 - Strane , et al. October 19, 2
2004-10-19
Self-aligned borderless contacts
App 20040104409 - Strane, Jay W. ;   et al.
2004-06-03
Low Cu percentages for reducing shorts in AlCu lines
App 20040020891 - Iggulden, Roy C. ;   et al.
2004-02-05
Self-aligned borderless contacts
App 20030228752 - Strane, Jay W. ;   et al.
2003-12-11

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