Strain; Robert J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Strain; Robert J..The latest application filed is for "reduced variation mosfet using a drain-extension-last process".
- Strain; Robert J. - San Jose CA
| Patent | Date |
|---|---|
| FFT-dram Grant 11,373,696 - Thomas , et al. June 28, 2 | 2022-06-28 |
| Fluctuation resistant FinFET Grant 9,847,404 - Strain , et al. December 19, 2 | 2017-12-19 |
| Reduced Variation MOSFET Using a Drain-Extension-Last Process App 20160260816 - Kapoor; Ashok K. ; et al. | 2016-09-08 |
| Reduced variation MOSFET using a drain-extension-last process Grant 9,379,214 - Kapoor , et al. June 28, 2 | 2016-06-28 |
| Reduced Variation MOSFET Using a Drain-Extension-Last Process App 20150236117 - Kapoor; Ashok K. ; et al. | 2015-08-20 |
| Fluctuation Resistant FinFET App 20150008490 - Strain; Robert J. ; et al. | 2015-01-08 |
| Random Doping Fluctuation Resistant FinFET App 20140103437 - Kapoor; Ashok K. ; et al. | 2014-04-17 |
| Gate defined Schottky diode Grant 7,544,557 - Levin , et al. June 9, 2 | 2009-06-09 |
| Cobalt silicide schottky diode on isolated well Grant 7,485,941 - Levin , et al. February 3, 2 | 2009-02-03 |
| Cobalt silicide schottky diode on isolated well App 20060125040 - Levin; Sharon ; et al. | 2006-06-15 |
| Gate defined schottky diode App 20060125019 - Levin; Sharon ; et al. | 2006-06-15 |
| Mask programmable read-only memory (ROM) cell Grant 6,809,948 - Nachumovsky , et al. October 26, 2 | 2004-10-26 |
| Multi-bit programmable memory cell having multiple anti-fuse elements App 20030223291 - Nachumovsky, Ishai ; et al. | 2003-12-04 |
| Multi-bit programmable memory cell having multiple anti-fuse elements Grant 6,590,797 - Nachumovsky , et al. July 8, 2 | 2003-07-08 |
| Tuneable microelectromechanical system resonator Grant 5,729,075 - Strain March 17, 1 | 1998-03-17 |
| Multiple gap read/write head for data storage devices Grant 5,644,457 - Llewellyn , et al. July 1, 1 | 1997-07-01 |
| Defect-free bipolar process Grant 5,453,389 - Strain , et al. September 26, 1 | 1995-09-26 |
| CMOS circuit having a reduced tendency to latch Grant 4,728,998 - Strain March 1, 1 | 1988-03-01 |
| Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions Grant 4,603,471 - Strain August 5, 1 | 1986-08-05 |
| Process for fabricating optical wave-guiding components and components made by the process Grant 4,585,299 - Strain April 29, 1 | 1986-04-29 |
| Ion implantation to increase emitter energy gap in bipolar transistors Grant 4,559,696 - Anand , et al. December 24, 1 | 1985-12-24 |
| Identification of repaired integrated circuits Grant 4,480,199 - Varshney , et al. October 30, 1 | 1984-10-30 |
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