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Vertically-constructed, temperature-sensing resistors and methods of making the same
Grant 10,937,574 - Cestra , et al. March 2, 2 | 2021-03-02 |
Dynamic biasing to mitigate electrical stress in integrated resistors
Grant 10,748,818 - Chatterjee , et al. A | 2020-08-18 |
Dynamic Biasing To Mitigate Electrical Stress In Integrated Resistors
App 20200203230 - Chatterjee; Tathagata ; et al. | 2020-06-25 |
Vertically-constructed, Temperature-sensing Resistors And Methods Of Making The Same
App 20200013528 - Cestra; Gregory Keith ; et al. | 2020-01-09 |
Vertically-constructed, temperature-sensing resistors and methods of making the same
Grant 10,431,357 - Cestra , et al. O | 2019-10-01 |
Vertically-constructed, Temperature-sensing Resistors And Methods Of Making The Same
App 20190148041 - Cestra; Gregory Keith ; et al. | 2019-05-16 |
Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance density
Grant 8,664,076 - Raghavan , et al. March 4, 2 | 2014-03-04 |
Data retention in a single poly EPROM cell
Grant 8,541,863 - Raghavan , et al. September 24, 2 | 2013-09-24 |
Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding device
Grant 8,445,353 - Raghavan , et al. May 21, 2 | 2013-05-21 |
Method Of Forming A Robust, Modular Mim Capacitor With Improved Capacitance Density
App 20130069200 - Raghavan; Venkat ; et al. | 2013-03-21 |
Data Retention In A Single Poly Eprom Cell
App 20120132975 - Raghavan; Venkat ; et al. | 2012-05-31 |
Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
Grant 8,086,979 - Brisbin , et al. December 27, 2 | 2011-12-27 |
Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in
App 20090254872 - Brisbin; Douglas ; et al. | 2009-10-08 |
Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
Grant 7,560,348 - Brisbin , et al. July 14, 2 | 2009-07-14 |
Method of forming a MIM capacitor
Grant 7,510,944 - Raghavan , et al. March 31, 2 | 2009-03-31 |
EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion
Grant 7,425,741 - Strachan , et al. September 16, 2 | 2008-09-16 |
Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
App 20070264768 - Brisbin; Douglas ; et al. | 2007-11-15 |
Method of improving the breakdown voltage of a diffused semiconductor junction
Grant 7,192,853 - Strachan , et al. March 20, 2 | 2007-03-20 |
PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in and method for designing and manufacturing such device
Grant 7,180,140 - Brisbin , et al. February 20, 2 | 2007-02-20 |
Layout optimization of integrated trench VDMOS arrays
Grant 7,071,513 - Dyer , et al. July 4, 2 | 2006-07-04 |
Integration of trench power transistors into a 1.5 .mu.m BCD process
Grant 7,067,879 - Dyer , et al. June 27, 2 | 2006-06-27 |
Low cost, high density diffusion diode-capacitor
Grant 6,798,641 - Hopper , et al. September 28, 2 | 2004-09-28 |
Method of forming contact to poly-filled trench isolation region
Grant 6,646,320 - Strachan November 11, 2 | 2003-11-11 |
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