Strach; Thomas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Strach; Thomas.The latest application filed is for "fine resolution on-chip voltage simulation to prevent under voltage conditions".

Company Profile

9.20.17

Strach; Thomas - Wildberg DE
Strach; Thomas - Boeblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Predictive on-chip voltage simulation to detect near-future under voltage conditions Grant 11,112,846 - Strach , et al. September 7, 2	2021-09-07
Discrete electronic device embedded in chip module Grant 10,734,317 - Huber , et al.	2020-08-04
Distributed on chip network to mitigate voltage droops Grant 10,725,517 - Lobo , et al.	2020-07-28
Fine Resolution On-chip Voltage Simulation To Prevent Under Voltage Conditions App 20200201413 - Strach; Thomas ; et al.	2020-06-25
Predictive On-chip Voltage Simulation To Detect Near-future Under Voltage Conditions App 20200201407 - Strach; Thomas ; et al.	2020-06-25
Distributed On Chip Network To Mitigate Voltage Droops App 20200033927 - Lobo; Preetham M. ; et al.	2020-01-30
Distributed on chip network to mitigate voltage droops Grant 10,481,662 - Lobo , et al. Nov	2019-11-19
Mitigating power noise using a current supply Grant 10,461,715 - Schmidt , et al. Oc	2019-10-29
Discrete Electronic Device Embedded In Chip Module App 20190295938 - Huber; Andreas ; et al.	2019-09-26
Discrete electronic device embedded in chip module Grant 10,354,946 - Huber , et al. July 16, 2	2019-07-16
Increasing the resolution of on-chip measurement circuits Grant 10,145,892 - Franch , et al. De	2018-12-04
Method for embedding a discrete electrical device in a printed circuit board Grant 10,149,388 - Chamberlin , et al. De	2018-12-04
Layout effect characterization for integrated circuits Grant 10,114,914 - Eckert , et al. October 30, 2	2018-10-30
Discrete Electronic Device Embedded In Chip Module App 20180228028 - Huber; Andreas ; et al.	2018-08-09
Discrete electronic device embedded in chip module Grant 9,980,385 - Huber , et al. May 22, 2	2018-05-22
Layout Effect Characterization For Integrated Circuits App 20180107771 - Eckert; Martin ; et al.	2018-04-19
Distributed On Chip Network To Mitigate Voltage Droops App 20180088650 - Lobo; Preetham M. ; et al.	2018-03-29
Layout effect characterization for integrated circuits Grant 9,904,748 - Eckert , et al. February 27, 2	2018-02-27
Increasing The Resolution Of On-chip Measurement Circuits App 20180052200 - FRANCH; ROBERT L. ; et al.	2018-02-22
Discrete Electronic Device Embedded In Chip Module App 20180027659 - Huber; Andreas ; et al.	2018-01-25
Embedding a discrete electrical device in a printed circuit board Grant 9,839,131 - Chamberlin , et al. December 5, 2	2017-12-05
Power noise histogram of a computer system Grant 9,804,231 - Eckert , et al. October 31, 2	2017-10-31
Layout effect characterization for integrated circuits Grant 9,740,813 - Eckert , et al. August 22, 2	2017-08-22
De-coupling capacitance placement Grant 9,684,759 - Barowski , et al. June 20, 2	2017-06-20
De-coupling capacitance placement Grant 9,679,099 - Barowski , et al. June 13, 2	2017-06-13
Discrete electronic device embedded in chip module Grant 9,673,179 - Huber , et al. June 6, 2	2017-06-06
Embedding A Discrete Electrical Device In A Printed Circuit Board App 20170118844 - CHAMBERLIN; Bruce J. ; et al.	2017-04-27
Embedding A Discrete Electrical Device In A Printed Circuit Board App 20170118842 - CHAMBERLIN; Bruce J. ; et al.	2017-04-27
De-coupling Capacitance Placement App 20170004239 - Barowski; Harry ; et al.	2017-01-05
De-coupling Capacitance Placement App 20170004248 - Barowski; Harry ; et al.	2017-01-05
Reducing power grid noise in a processor while minimizing performance loss Grant 9,146,772 - Eisen , et al. September 29, 2	2015-09-29
Reducing power grid noise in a processor while minimizing performance loss Grant 9,141,421 - Eisen , et al. September 22, 2	2015-09-22
Power Noise Histogram Of A Computer System App 20140316725 - ECKERT; Martin ; et al.	2014-10-23
Reducing Power Grid Noise In A Processor While Minimizing Performance Loss App 20140157033 - Eisen; Lee E. ; et al.	2014-06-05
Reducing Power Grid Noise In A Processor While Minimizing Performance Loss App 20140157277 - Eisen; Lee E. ; et al.	2014-06-05
Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules Grant 7,266,788 - Haridass , et al. September 4, 2	2007-09-04
Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules App 20070022398 - Haridass; Anand ; et al.	2007-01-25

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