Storino; Salvatore N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Storino; Salvatore N..The latest application filed is for "state sensing system for efuse memory".

Company Profile

0.10.10

Storino; Salvatore N. - Rochester MN US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
State sensing system for eFuse memory Grant 8,780,604 - Liao , et al. July 15, 2	2014-07-15
State Sensing System For Efuse Memory App 20140003120 - Liao; Chihhung ; et al.	2014-01-02
SerDes double rate bitline with interlock to block precharge capture Grant 7,839,715 - Chang , et al. November 23, 2	2010-11-23
SerDes double rate bitline with interlock to block precharge capture App 20100106996 - Chang; Leland ; et al.	2010-04-29
Metal fill region of a semiconductor chip Grant 7,489,039 - Baumgartner , et al. February 10, 2	2009-02-10
Systems, Methods And Computer Products For Traversing Design Hierarchy Using A Scroll Mechanism App 20090024975 - Ladin; Karl L. ; et al.	2009-01-22
Traversing Graphical Layers Using A Scrolling Mechanism In A Physical Design Environment App 20080266246 - Ladin; Karl L. ; et al.	2008-10-30
Metal Fill Region Of A Semiconductor Chip App 20080079158 - Baumgartner; Steven J. ; et al.	2008-04-03
Design Structure for a Metal Fill Region of a Semiconductor Chip App 20080082300 - Baumgartner; Steven J. ; et al.	2008-04-03
Balanced single ended to differential signal converter Grant 7,142,061 - Storino November 28, 2	2006-11-28
Balanced single ended to differential signal converter App 20060158258 - Storino; Salvatore N.	2006-07-20
Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits Grant 6,808,998 - Storino , et al. October 26, 2	2004-10-26
Changing the thread capacity of a multithreaded computer processor Grant 6,748,556 - Storino , et al. June 8, 2	2004-06-08
Field protection against thread loss in a multithreaded computer processor Grant 6,681,345 - Storino , et al. January 20, 2	2004-01-20
Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits App 20010000921 - Storino, Salvatore N. ; et al.	2001-05-10
Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits App 20010000950 - Tran, Jeff Van ; et al.	2001-05-10
Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements Grant 6,188,247 - Storino , et al. February 13, 2	2001-02-13
Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance Grant 6,163,173 - Storino , et al. December 19, 2	2000-12-19

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