Stok; Leon
Patent Applications and Registrations
Patent applications and USPTO patent grants for Stok; Leon.The latest application filed is for "circuit layout similarity metric for semiconductor testsite coverage".
- Stok; Leon - Croton-on-Hudson NY
- Stok; Leon - Mount Kisco NY
| Patent | Date |
|---|---|
| Circuit Layout Similarity Metric For Semiconductor Testsite Coverage App 20200364316 - Topaloglu; Rasit Onur ; et al. | 2020-11-19 |
| Circuit layout similarity metric for semiconductor testsite coverage Grant 10,839,133 - Topaloglu , et al. November 17, 2 | 2020-11-17 |
| Physical design system and method Grant 8,473,885 - Cohn , et al. June 25, 2 | 2013-06-25 |
| Physical design system and method Grant 8,219,943 - Cohn , et al. July 10, 2 | 2012-07-10 |
| Physical Design System And Method App 20120167029 - Cohn; John M. ; et al. | 2012-06-28 |
| Iphysical Design System And Method App 20090204930 - Cohn; John M. ; et al. | 2009-08-13 |
| Physical design system and method Grant 7,536,664 - Cohn , et al. May 19, 2 | 2009-05-19 |
| Method for performing timing closure on VLSI chips in a distributed environment Grant 7,178,120 - Hieter , et al. February 13, 2 | 2007-02-13 |
| Method and apparatus for applying fine-grained transforms during placement synthesis interaction Grant 7,047,163 - Chakraborty , et al. May 16, 2 | 2006-05-16 |
| Physical design system and method App 20060036977 - Cohn; John M. ; et al. | 2006-02-16 |
| CMOS tapered gate and synthesis method Grant 6,966,046 - Curran , et al. November 15, 2 | 2005-11-15 |
| Method for performing timing closure on VLSI chips in a distributed environment App 20040133860 - Hieter, Nathaniel ; et al. | 2004-07-08 |
| CMOS tapered gate and synthesis method App 20020157079 - Curran, Brian W. ; et al. | 2002-10-24 |
| Method and apparatus for logic synthesis employing size independent timing optimization Grant 6,167,557 - Kudva , et al. December 26, 2 | 2000-12-26 |
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