Stoek; Thomas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Stoek; Thomas.The latest application filed is for "molded semiconductor module having a mold step for increasing creepage distance".

Company Profile

13.10.15

Stoek; Thomas - Buxtehude DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Molded Semiconductor Module Having A Mold Step For Increasing Creepage Distance App 20220262693 - Kreiter; Oliver Markus ; et al.	2022-08-18
Metal Clip With Solder Volume Balancing Reservoir App 20220238475 - Stoek; Thomas ; et al.	2022-07-28
Leadframe Package With Adjustable Clip App 20220189855 - FEUERBAUM; Christian ; et al.	2022-06-16
Power Semiconductor Package And Method For Fabricating A Power Semiconductor Package App 20220115245 - Narayanasamy; Jayaganasan ; et al.	2022-04-14
Double-sided cooled molded semiconductor package Grant 11,302,613 - Chiang , et al. April 12, 2	2022-04-12
Semiconductor arrangement, laminated semiconductor arrangement and method for fabricating a semiconductor arrangement Grant 11,183,445 - Ahlers , et al. November 23, 2	2021-11-23
Molded Semiconductor Package Having A Negative Standoff App 20210358836 - Stoek; Thomas ; et al.	2021-11-18
Semiconductor package having leads with a negative standoff Grant 11,101,201 - Stoek , et al. August 24, 2	2021-08-24
Multi-branch terminal for integrated circuit (IC) package Grant 10,971,436 - Stoek , et al. April 6, 2	2021-04-06
Double-Sided Cooled Molded Semiconductor Package App 20210020550 - Chiang; Chau Fatt ; et al.	2021-01-21
Molded Semiconductor Package with Double-Sided Cooling App 20210020547 - Chiang; Chau Fatt ; et al.	2021-01-21
Molded semiconductor package with double-sided cooling Grant 10,886,199 - Chiang , et al. January 5, 2	2021-01-05
Semiconductor Arrangement, Laminated Semiconductor Arrangement And Method For Fabricating A Semiconductor Arrangement App 20200279799 - AHLERS; Dirk ; et al.	2020-09-03
Semiconductor Package Having Leads with a Negative Standoff App 20200279795 - Stoek; Thomas ; et al.	2020-09-03
Semiconductor Package, Metal Sheet for Use in a Semiconductor Package, and Method for Producing a Semiconductor Package App 20200185301 - Stoek; Thomas ; et al.	2020-06-11
Selective plating of semiconductor package leads Grant 10,651,109 - Abd Hamid , et al.	2020-05-12
Multi-branch Terminal For Integrated Circuit (ic) Package App 20200020618 - STOEK; Thomas ; et al.	2020-01-16
Selective Plating of Semiconductor Package Leads App 20200020607 - Abd Hamid; Syahir ; et al.	2020-01-16
Multi-branch terminal for integrated circuit (IC) package Grant 10,354,943 - Stoek , et al. July 16, 2	2019-07-16
Semiconductor package with leadframe Grant 10,319,671 - Ahlers , et al.	2019-06-11
Semiconductor package for multiphase circuitry device Grant 10,147,703 - Macheiner , et al. De	2018-12-04
Semiconductor Chip Package Having a Cooling Surface and Method of Manufacturing a Semiconductor Package App 20180342438 - Chen; Liu ; et al.	2018-11-29
Semiconductor Package with Leadframe App 20180342447 - Ahlers; Dirk ; et al.	2018-11-29
Semiconductor Package For Multiphase Circuitry Device App 20180277513 - Macheiner; Stefan ; et al.	2018-09-27
Transistor package with terminals coupled via chip carrier Grant 9,978,672 - Ahlers , et al. May 22, 2	2018-05-22

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