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Patent applications and USPTO patent grants for STIFFLER; Scott R..The latest application filed is for "device with decreased pitch contact to active regions".
Patent | Date |
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Device With Decreased Pitch Contact To Active Regions App 20180261512 - GREENE; Brian J. ;   et al. | 2018-09-13 |
Device with decreased pitch contact to active regions Grant 10,074,571 - Greene , et al. September 11, 2 | 2018-09-11 |
Deep trench sidewall etch stop Grant 9,748,250 - Hoyos , et al. August 29, 2 | 2017-08-29 |
Multiple Patterning Method For Substrate App 20170170016 - Lee; Woo-Hyeong ;   et al. | 2017-06-15 |
Deep Trench Sidewall Etch Stop App 20160358954 - Hoyos; Diego A. ;   et al. | 2016-12-08 |
Bulk finFET well contacts with fin pattern uniformity Grant 9,240,352 - Anderson , et al. January 19, 2 | 2016-01-19 |
Substrate Local Interconnect Integration With Finfets App 20150145041 - Divakaruni; Ramachandra ;   et al. | 2015-05-28 |
Bulk Finfet Well Contacts With Fin Pattern Uniformity App 20140110767 - ANDERSON; Brent A. ;   et al. | 2014-04-24 |
Silicon-on-insulator vertical array device trench capacitor DRAM Grant 6,566,177 - Radens , et al. May 20, 2 | 2003-05-20 |
Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Grant 6,426,252 - Radens , et al. July 30, 2 | 2002-07-30 |
Electronic switch for decoupling capacitor Grant 6,307,250 - Krauter , et al. October 23, 2 | 2001-10-23 |
Method for forming capacitors with roughened single crystal plates Grant 5,384,152 - Chu , et al. January 24, 1 | 1995-01-24 |
Isolation technique for silicon germanium devices Grant 5,266,813 - Comfort , et al. November 30, 1 | 1993-11-30 |
Capacitors with roughened single crystal plates Grant 5,245,206 - Chu , et al. September 14, 1 | 1993-09-14 |
Method of fabricating silicon-on-insulator transistors with a shared element Grant 4,649,627 - Abernathey , et al. March 17, 1 | 1987-03-17 |
Method of producing a thin silicon-on-insulator layer Grant 4,601,779 - Abernathey , et al. July 22, 1 | 1986-07-22 |
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