Stief; Reidar
Patent Applications and Registrations
Patent applications and USPTO patent grants for Stief; Reidar.The latest application filed is for "circuit configuration for receiving a data signal".
- Stief; Reidar - Munchen DE
| Patent | Date |
|---|---|
| Circuit configuration for receiving a data signal Grant 7,327,766 - Stief February 5, 2 | 2008-02-05 |
| Circuit for synchronizing signals during the exchange of information between circuits Grant 6,774,688 - Rohleder , et al. August 10, 2 | 2004-08-10 |
| Integrated memory and method for testing an integrated memory Grant 6,639,861 - Stief , et al. October 28, 2 | 2003-10-28 |
| Delay locked loop Grant 6,586,978 - Stief July 1, 2 | 2003-07-01 |
| Circuit configuration for receiving a data signal App 20030053471 - Stief, Reidar | 2003-03-20 |
| Delay locked loop App 20030011412 - Stief, Reidar | 2003-01-16 |
| Integrated memory circuit and method for reading a data item from a memory cell App 20030002351 - Beer, Peter ; et al. | 2003-01-02 |
| Circuit for synchronizing signals during the exchange of information between circuits App 20020158677 - Rohleder, Markus ; et al. | 2002-10-31 |
| Integrated memory and method for testing an integrated memory App 20020154560 - Stief, Reidar ; et al. | 2002-10-24 |
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