Stevens; Kenneth S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Stevens; Kenneth S..The latest application filed is for "asynchronous finite state machines".

Company Profile

1.12.15

Stevens; Kenneth S. - Salt Lake City UT
Stevens; Kenneth S. - Brighton UT
Stevens; Kenneth S. - Hillsboro OR
Stevens; Kenneth S. - Union City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Asynchronous finite state machines Grant 10,310,994 - Stevens , et al.	2019-06-04
Relative timed clock gating cell Grant 10,084,434 - Stevens , et al. September 25, 2	2018-09-25
Asynchronous Finite State Machines App 20180246819 - Stevens; Kenneth S. ; et al.	2018-08-30
Relative timing characterization Grant 9,953,120 - Stevens April 24, 2	2018-04-24
Clock gating with an asynchronous wrapper cell Grant 9,753,486 - Stevens , et al. September 5, 2	2017-09-05
Relative Timed Clock Gating Cell App 20170244392 - Stevens; Kenneth S. ; et al.	2017-08-24
Relative timed clock gating cell Grant 9,548,736 - Stevens , et al. January 17, 2	2017-01-17
Relative Timed Clock Gating Cell App 20160365857 - Stevens; Kenneth S. ; et al.	2016-12-15
Clock Gating With An Asynchronous Wrapper Cell App 20160363955 - Stevens; Kenneth S. ; et al.	2016-12-15
Relative Timing Characterization App 20150026653 - STEVENS; KENNETH S.	2015-01-22
Relative Timing Architecture App 20140165022 - STEVENS; KENNETH S.	2014-06-12
Cycle Cutting With Timing Path Analysis App 20130097567 - Stevens; Kenneth S. ; et al.	2013-04-18
Cycle cutting with timing path analysis Grant 8,365,116 - Stevens , et al. January 29, 2	2013-01-29
Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verification Grant 8,321,825 - Stevens , et al. November 27, 2	2012-11-27
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification App 20120254815 - Stevens; Kenneth S. ; et al.	2012-10-04
Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verification Grant 8,239,796 - Stevens , et al. August 7, 2	2012-08-07
Cycle Cutting With Timing Path Analysis App 20120144359 - Stevens; Kenneth S. ; et al.	2012-06-07
Method and system for asynchronous chip design Grant 8,065,647 - Stevens November 22, 2	2011-11-22
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification App 20110161902 - Stevens; Kenneth S. ; et al.	2011-06-30
Method And System For Asynchronous Chip Design App 20090106719 - Stevens; Kenneth S.	2009-04-23
Algorithm for finding vectors to stimulate all paths and arcs through an LVS gate Grant 6,557,149 - Morrise , et al. April 29, 2	2003-04-29
An algorithm for finding vectors to stimulate all paths and arcs through an LVS gate App 20020145433 - Morrise, Matthew C. ; et al.	2002-10-10
Apparatus for multi-processor communications Grant 4,922,408 - Davis , et al. May 1, 1	1990-05-01

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