Stern; Kenneth J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Stern; Kenneth J..The latest application filed is for "precision set-reset logic circuit and method".
- Stern; Kenneth J. - Watertown MA
- Stern, Kenneth J. - Newton MA
- Stern; Kenneth J. - Austin TX
| Patent | Date |
|---|---|
| Timing vernier architecture for generating high speed, high accuracy timing edges Grant 6,774,694 - Stern , et al. August 10, 2 | 2004-08-10 |
| Precision SET-RESET logic circuit and method App 20020024370 - Gaiser, Thomas A. ; et al. | 2002-02-28 |
| Programmable delay circuit and method with dummy circuit compensation Grant 6,242,959 - Stern June 5, 2 | 2001-06-05 |
| Clock multiplier/jitter attenuator Grant 5,150,386 - Stern , et al. * September 22, 1 | 1992-09-22 |
| Low power output stage circuitry in an amplifier Grant 4,988,954 - Stern , et al. January 29, 1 | 1991-01-29 |
| Linear jitter attenuator Grant 4,941,156 - Stern , et al. July 10, 1 | 1990-07-10 |
| Clock multiplier/jitter attenuator Grant 4,805,198 - Stern , et al. February 14, 1 | 1989-02-14 |
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