Patent | Date |
---|
Real Time Input/output Address Translation For Virtualized Systems App 20210165744 - GOVINDARAJAN; Sriramakrishnan ;   et al. | 2021-06-03 |
Real time input/output address translation for virtualized systems Grant 10,949,357 - Govindarajan , et al. March 16, 2 | 2021-03-16 |
Real Time Input/output Address Translation For Virtualized Systems App 20200242048 - GOVINDARAJAN; Sriramakrishnan ;   et al. | 2020-07-30 |
Reduced stack usage in a multithreaded processor Grant 10,649,786 - Steiss | 2020-05-12 |
Reduced Stack Usage In A Multithreaded Processor App 20180157493 - STEISS; Donald E. | 2018-06-07 |
System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions Grant 9,176,739 - Steiss November 3, 2 | 2015-11-03 |
System And Method For Instruction Sets With Run-time Consistency Check App 20130036294 - Steiss; Donald E. | 2013-02-07 |
Thread interleaving in a multithreaded embedded processor Grant 8,245,014 - Steiss , et al. August 14, 2 | 2012-08-14 |
Translation look-aside buffer with variable page sizes Grant 8,156,309 - Steiss April 10, 2 | 2012-04-10 |
Descriptor transfer logic Grant 7,739,426 - Steiss , et al. June 15, 2 | 2010-06-15 |
Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor Grant 7,551,617 - Eatherton , et al. June 23, 2 | 2009-06-23 |
Translation Look-aside Buffer With Variable Page Sizes App 20090106523 - Steiss; Donald E. | 2009-04-23 |
Thread Interleaving In A Multithreaded Embedded Processor App 20090049279 - Steiss; Donald E. ;   et al. | 2009-02-19 |
Thread-aware instruction fetching in a multithreaded embedded processor Grant 7,441,101 - Steiss , et al. October 21, 2 | 2008-10-21 |
Multi-threaded packeting processing architecture App 20060179156 - Eatherton; Will ;   et al. | 2006-08-10 |
Sub-pipelined and pipelined execution in a VLIW Grant 6,895,494 - Steiss , et al. May 17, 2 | 2005-05-17 |
System and method for processing data in an integrated circuit environment Grant 6,895,493 - Steiss , et al. May 17, 2 | 2005-05-17 |
Flip flop with reduced leakage current Grant 6,781,411 - Steiss , et al. August 24, 2 | 2004-08-24 |
Microprocessor with conditional cross path stall to minimize CPU cycle time length Grant 6,766,440 - Steiss , et al. July 20, 2 | 2004-07-20 |
System and method for processing data in an integrated circuit environment App 20040019764 - Steiss, Donald E. ;   et al. | 2004-01-29 |
Flip flop with reduced leakage current App 20030141911 - Steiss, Donald E. ;   et al. | 2003-07-31 |
Single event upset tolerant microprocessor architecture Grant 6,571,363 - Steiss May 27, 2 | 2003-05-27 |
Microprocessor with non-aligned memory access Grant 6,539,467 - Anderson , et al. March 25, 2 | 2003-03-25 |
Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory App 20010018745 - Laczko, Frank L. SR. ;   et al. | 2001-08-30 |
Secure computing device including operating system stored in non-relocatable page of memory Grant 6,266,754 - Laczko, Sr. , et al. July 24, 2 | 2001-07-24 |
Shared floating-point unit in a single chip multiprocessor Grant 6,148,395 - Dao , et al. November 14, 2 | 2000-11-14 |
Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register Grant 6,065,113 - Shiell , et al. May 16, 2 | 2000-05-16 |
Circuits, systems, and methods for external evaluation of microprocessor built-in self-test Grant 6,061,811 - Bondi , et al. May 9, 2 | 2000-05-09 |
Pipelined microprocessor with efficient self-modifying code detection and handling Grant 6,009,516 - Steiss , et al. December 28, 1 | 1999-12-28 |
Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes Grant 5,961,632 - Shiell , et al. October 5, 1 | 1999-10-05 |
Multi-stream complex instruction set microprocessor Grant 5,913,049 - Shiell , et al. June 15, 1 | 1999-06-15 |
Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return Grant 5,850,543 - Shiell , et al. December 15, 1 | 1998-12-15 |
Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays Grant 5,838,908 - Matzke , et al. November 17, 1 | 1998-11-17 |