Steegen; An L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Steegen; An L..The latest application filed is for "method and structure for forming strained si for cmos devices".

Company Profile

0.21.19

Steegen; An L. - Hopewell Junction NY
Steegen; An L. - Stamford CT
Steegen; An L. - Stanford CT
Steegen; An L - Stamford CT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and structure for forming strained SI for CMOS devices Grant 7,928,443 - Steegen , et al. April 19, 2	2011-04-19
Selective silicon-on-insulator isolation structure and method Grant 7,923,786 - Steegen , et al. April 12, 2	2011-04-12
Method And Structure For Forming Strained Si For Cmos Devices App 20100109048 - STEEGEN; An L. ; et al.	2010-05-06
Method and structure for forming strained Si for CMOS devices Grant 7,700,951 - Steegen , et al. April 20, 2	2010-04-20
CMOS silicide metal gate integration Grant 7,655,557 - Amos , et al. February 2, 2	2010-02-02
Method and structure for forming strained SI for CMOS devices Grant 7,550,338 - Steegen , et al. June 23, 2	2009-06-23
Method And Structure For Forming Strained Si For Cmos Devices App 20080283824 - STEEGEN; An L. ; et al.	2008-11-20
Cmos Silicide Metal Gate Integration App 20080254622 - Amos; Ricky S. ; et al.	2008-10-16
Method and structure for forming strained SI for CMOS devices Grant 7,429,752 - Steegen , et al. September 30, 2	2008-09-30
CMOS silicide metal gate integration Grant 7,411,227 - Amos , et al. August 12, 2	2008-08-12
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 7,396,714 - Chen , et al. July 8, 2	2008-07-08
Selective Silicon-on-insulator Isolation Structure And Method App 20080029818 - Steegen; An L. ; et al.	2008-02-07
Selective silicon-on-insulator isolation structure and method Grant 7,326,983 - Steegen , et al. February 5, 2	2008-02-05
Method And Structure For Forming Strained Si For Cmos Devices App 20080003735 - STEEGEN; An L. ; et al.	2008-01-03
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 7,291,528 - Chen , et al. November 6, 2	2007-11-06
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions App 20070249114 - Chen; Huajie ; et al.	2007-10-25
Method and structure for forming strained Si for CMOS devices Grant 7,129,126 - Steegen , et al. October 31, 2	2006-10-31
Method for forming self-aligned dual salicide in CMOS technologies Grant 7,112,481 - Fang , et al. September 26, 2	2006-09-26
CMOS silicide metal gate integration App 20060189061 - Amos; Ricky S. ; et al.	2006-08-24
Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow Grant 7,081,397 - Baiocco , et al. July 25, 2	2006-07-25
Method for forming self-aligned dual salicide in CMOS technologies Grant 7,067,368 - Fang , et al. June 27, 2	2006-06-27
Method for forming self-aligned dual salicide in CMOS technologies Grant 7,064,025 - Fang , et al. June 20, 2	2006-06-20
Method For Forming Self-aligned Dual Salicide In Cmos Technologies App 20060121662 - Fang; Sunfei ; et al.	2006-06-08
Method for forming self-aligned dual salicide in CMOS technologies App 20060121664 - Fang; Sunfei ; et al.	2006-06-08
Method For Forming Self-aligned Dual Salicide In Cmos Technologies App 20060121665 - Fang; Sunfei ; et al.	2006-06-08
CMOS silicide metal gate integration Grant 7,056,782 - Amos , et al. June 6, 2	2006-06-06
Trench sidewall passivation for lateral rie in a selective silicon-on-insulator process flow App 20060046428 - Baiocco; Christopher V. ; et al.	2006-03-02
Selective silicon-on-insulator isolation structure and method Grant 6,936,522 - Steegen , et al. August 30, 2	2005-08-30
CMOS silicide metal gate integration App 20050186747 - Amos, Ricky S. ; et al.	2005-08-25
Method for integration of silicide contacts and silicide gate metals Grant 6,927,117 - Cabral, Jr. , et al. August 9, 2	2005-08-09
Selective silicon-on-insulator isolation structure and method App 20050164468 - Steegen, An L. ; et al.	2005-07-28
Method for forming metal replacement gate of high performance Grant 6,921,711 - Cabral, Jr. , et al. July 26, 2	2005-07-26
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions App 20050158931 - Chen, Huajie ; et al.	2005-07-21
Method for integration of silicide contacts and silicide gate metals App 20050118757 - Cabral, Cyril JR. ; et al.	2005-06-02
Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 6,891,192 - Chen , et al. May 10, 2	2005-05-10
METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES App 20050093076 - Steegen, An L. ; et al.	2005-05-05
Silicide Proximity Structures For Cmos Device Performance Improvements App 20050064687 - Chidambarrao, Dureseti ; et al.	2005-03-24
Silicide proximity structures for CMOS device performance improvements Grant 6,869,866 - Chidambarrao , et al. March 22, 2	2005-03-22
Structure And Method For Metal Replacement Gate Of High Performance App 20050051854 - Cabral, Cyril JR. ; et al.	2005-03-10
Structure And Method Of Making Strained Semiconductor Cmos Transistors Having Lattice-mismatched Source And Drain Regions App 20050029601 - Chen, Huajie ; et al.	2005-02-10

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