Starke; William John

Patent Applications and Registrations

Patent applications and USPTO patent grants for Starke; William John.The latest application filed is for "information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow".

Company Profile

0.90.74

Starke; William John - Round Rock TX US
Starke; William John - Round Rouck TX
Starke; William John - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Information handling system with immediate scheduling of load operations Grant 10,489,293 - Ghai , et al. Nov	2019-11-26
Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing Grant 8,433,851 - Clark , et al. April 30, 2	2013-04-30
Processor system and methods of triggering a block move using a system bus write command initiated by user code Grant 8,281,075 - Arimilli , et al. October 2, 2	2012-10-02
Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline Grant 8,230,117 - Daly, Jr. , et al. July 24, 2	2012-07-24
Data processing system and method for efficient coherency communication utilizing coherency domain indicators Grant 8,230,178 - Fields, Jr. , et al. July 24, 2	2012-07-24
Dynamic runtime modification of array layout for offset Grant 8,214,592 - Arimilli , et al. July 3, 2	2012-07-03
Data processing system and method for efficient coherency communication utilizing coherency domains Grant 8,214,600 - Fields, Jr. , et al. July 3, 2	2012-07-03
Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow Grant 8,195,880 - Gai , et al. June 5, 2	2012-06-05
Chaining multiple smaller store queue entries for more efficient store queue usage Grant 8,166,246 - Guthrie , et al. April 24, 2	2012-04-24
Specifying an access hint for prefetching partial cache block data in a cache hierarchy Grant 8,140,759 - Frey , et al. March 20, 2	2012-03-20
Information handling system with immediate scheduling of load operations and fine-grained access to cache memory Grant 8,140,756 - Gai , et al. March 20, 2	2012-03-20
Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow Grant 8,140,765 - Gai , et al. March 20, 2	2012-03-20
System bus structure for large L2 cache array topology with different latency domains Grant 8,015,358 - Chung , et al. September 6, 2	2011-09-06
L2 cache controller with slice directory and unified cache structure Grant 8,001,330 - Clark , et al. August 16, 2	2011-08-16
Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation Grant 7,987,320 - Bell, Jr. , et al. July 26, 2	2011-07-26
Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller Grant 7,917,730 - Marino , et al. March 29, 2	2011-03-29
Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers Grant 7,913,123 - Al-Omari , et al. March 22, 2	2011-03-22
Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements Grant 7,865,650 - Marino , et al. January 4, 2	2011-01-04
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states Grant 7,849,298 - Arimilli , et al. December 7, 2	2010-12-07
Victim cache using direct intervention Grant 7,827,354 - Clark , et al. November 2, 2	2010-11-02
Information Handling System With Immediate Scheduling Of Load Operations In A Dual-bank Cache With Dual Dispatch Into Write/read Data Flow App 20100268887 - Ghai; Sanjeev ; et al.	2010-10-21
Information Handling System With Immediate Scheduling Of Load Operations App 20100268895 - Ghai; Sanjeev ; et al.	2010-10-21
Dynamic Runtime Modification of Array Layout for Offset App 20100268880 - Arimilli; Ravi Kumar ; et al.	2010-10-21
Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory App 20100268883 - Ghai; Sanjeev ; et al.	2010-10-21
Specifying An Access Hint For Prefetching Partial Cache Block Data In A Cache Hierarchy App 20100268886 - Frey; Bradly George ; et al.	2010-10-21
Load Request Scheduling In A Cache Hierarchy App 20100268882 - Cargnoni; Robert Alan ; et al.	2010-10-21
Information Handling System With Immediate Scheduling Of Load Operations In A Dual-bank Cache With Single Dispatch Into Write/read Data Flow App 20100268890 - Ghai; Sanjeev ; et al.	2010-10-21
Techniques For Write-after-write Ordering In A Coherency Managed Processor System That Employs A Command Pipeline App 20100262720 - Daly, JR.; George William ; et al.	2010-10-14
Techniques For Triggering A Block Move Using A System Bus Write Command Initiated By User Code App 20100262735 - Arimilli; Lakshminarayana Baba ; et al.	2010-10-14
System bus structure for large L2 cache array topology with different latency domains Grant 7,793,048 - Chung , et al. September 7, 2	2010-09-07
Cache coherent I/O communication Grant 7,783,842 - Arimilli , et al. August 24, 2	2010-08-24
L2 cache array topology for large cache with different latency domains Grant 7,783,834 - Clark , et al. August 24, 2	2010-08-24
Efficient coherency communication utilizing an IG coherency state Grant 7,783,841 - Fields, Jr. , et al. August 24, 2	2010-08-24
Data processing system and method for efficient coherency communication utilizing coherency domain indicators Grant 7,774,555 - Fields, Jr. , et al. August 10, 2	2010-08-10
Cache member protection with partial make MRU allocation Grant 7,689,777 - Bell, Jr. , et al. March 30, 2	2010-03-30
Information Handling System Including A Plurality Of Multiple Compute Element SMP Processors With Primary And Secondary Interconnect Trunks App 20090248940 - Marino; Charles Francis ; et al.	2009-10-01
Information Handling System Including Multiple Compute Element Processor With Primary And Secondary Interconnect Trunks App 20090248946 - Marino; Charles Francis ; et al.	2009-10-01
Data processing system and method for efficient communication utilizing an Ig coherency state Grant 7,584,329 - Fields, Jr. , et al. September 1, 2	2009-09-01
Method For Chaining Multiple Smaller Store Queue Entries For More Efficient Store Queue Usage App 20090198867 - Guthrie; Guy Lynn ; et al.	2009-08-06
Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States App 20090157945 - Arimilli; Ravi Kumar ; et al.	2009-06-18
Cache Mechanism And Method For Avoiding Cast Out On Bad Victim Select And Recycling Victim Select Operation App 20090150617 - BELL, JR.; ROBERT H. ; et al.	2009-06-11
L2 Cache Controller With Slice Directory And Unified Cache Structure App 20090083489 - Clark; Leo James ; et al.	2009-03-26
Data processing system and method for efficient L3 cache directory management Grant 7,500,065 - Guthrie , et al. March 3, 2	2009-03-03
Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing App 20090049248 - Clark; Leo James ; et al.	2009-02-19
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states Grant 7,493,478 - Arimilli , et al. February 17, 2	2009-02-17
L2 cache controller with slice directory and unified cache structure Grant 7,490,200 - Clark , et al. February 10, 2	2009-02-10
Data processing system and method for efficient L3 cache directory management Grant 7,490,202 - Guthrie , et al. February 10, 2	2009-02-10
Method, Apparatus, and Computer Program Product in a Processor for Dynamically During Runtime Allocating Memory for In-Memory Hardware Tracing App 20090031173 - Al-Omari; Ra'ed Mohammad ; et al.	2009-01-29
Apparatus and Computer Program Product in a Processor for Performing In-Memory Tracing Using Existing Communication Paths App 20090024878 - Al-Omari; Ra'ed Mohammad ; et al.	2009-01-22
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states Grant 7,480,772 - Fields, Jr. , et al. January 20, 2	2009-01-20
Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers App 20090006825 - Al-Omari; Ra'ed Mohammad ; et al.	2009-01-01
System Bus Structure For Large L2 Cache Array Topology With Different Latency Domains App 20090006759 - Chung; Vicente Enrique ; et al.	2009-01-01
System bus structure for large L2 cache array topology with different latency domains Grant 7,469,318 - Chung , et al. December 23, 2	2008-12-23
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states Grant 7,454,577 - Fields, Jr. , et al. November 18, 2	2008-11-18
Method in a processor for dynamically during runtime allocating memory for in-memory hardware tracing Grant 7,437,618 - Al-Omari , et al. October 14, 2	2008-10-14
Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers Grant 7,437,617 - Al-Omari , et al. October 14, 2	2008-10-14
Pipelining D States For Mru Steerage During Mru-lru Member Allocation App 20080244187 - BELL; ROBERT H. ; et al.	2008-10-02
Method in a processor for performing in-memory tracing using existing communication paths Grant 7,421,619 - Al-Omari , et al. September 2, 2	2008-09-02
Cache Member Protection With Partial Make Mru Allocation App 20080177953 - BELL; ROBERT H. ; et al.	2008-07-24
Pipelining D states for MRU steerage during MRU/LRU member allocation Grant 7,401,189 - Bell, Jr. , et al. July 15, 2	2008-07-15
L2 cache array topology for large cache with different latency domains Grant 7,366,841 - Clark , et al. April 29, 2	2008-04-29
Data Processing System and Method for Efficient L3 Cache Directory Management App 20080098177 - Guthrie; Guy Lynn ; et al.	2008-04-24
Cache member protection with partial make MRU allocation Grant 7,363,433 - Bell, Jr. , et al. April 22, 2	2008-04-22
Data Processing System and Method for Efficient L3 Cache Directory Management App 20080091885 - Guthrie; Guy Lynn ; et al.	2008-04-17
L2 Cache Array Topology For Large Cache With Different Latency Domains App 20080077740 - Clark; Leo James ; et al.	2008-03-27
Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation Grant 7,343,455 - Bell, Jr. , et al. March 11, 2	2008-03-11
Data Processing System And Method For Efficient Communication Utilizing An Ig Coherency State App 20080052471 - FIELDS, JR.; JAMES STEPHEN ; et al.	2008-02-28
Data processing system and method for efficient L3 cache directory management Grant 7,337,280 - Guthrie , et al. February 26, 2	2008-02-26
Victim Cache Using Direct Intervention App 20080046651 - Clark; Leo James ; et al.	2008-02-21
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states App 20080040556 - Fields; James Stephen JR. ; et al.	2008-02-14
Data Processing System And Method For Efficient Coherency Communication Utilizing Coherency Domain Indicators App 20080028155 - FIELDS; JAMES STEPHEN JR. ; et al.	2008-01-31
Half-good mode for large L2 cache array topology with different latency domains Grant 7,308,537 - Fields, Jr. , et al. December 11, 2	2007-12-11
Victim cache using direct intervention Grant 7,305,522 - Clark , et al. December 4, 2	2007-12-04
Cache memory direct intervention Grant 7,305,523 - Guthrie , et al. December 4, 2	2007-12-04
System and method of re-ordering store operations within a processor Grant 7,284,102 - Guthrie , et al. October 16, 2	2007-10-16
Cache directory array recovery mechanism to support special ECC stuck bit matrix Grant 7,272,773 - Cargnoni , et al. September 18, 2	2007-09-18
Cross partition sharing of state information Grant 7,272,664 - Arimilli , et al. September 18, 2	2007-09-18
Processor, data processing system and method for synchronizing access to data in shared memory Grant 7,228,385 - Guthrie , et al. June 5, 2	2007-06-05
Processor, data processing system and method for synchronizing access to data in shared memory Grant 7,200,717 - Guthrie , et al. April 3, 2	2007-04-03
Processor, data processing system and method for synchronzing access to data in shared memory Grant 7,197,604 - Guthrie , et al. March 27, 2	2007-03-27
System and method of responding to a cache read error with a temporary cache directory column delete App 20070022250 - Fields; James Stephen JR. ; et al.	2007-01-25
Managing processor architected state upon an interrupt Grant 7,117,319 - Arimilli , et al. October 3, 2	2006-10-03
Cache allocation mechanism for biasing subsequent allocations based upon cache directory state Grant 7,103,721 - Cargnoni , et al. September 5, 2	2006-09-05
Cache memory direct intervention App 20060184743 - Guthrie; Guy Lynn ; et al.	2006-08-17
Victim cache using direct intervention App 20060184742 - Clark; Leo James ; et al.	2006-08-17
Method, apparatus, and computer program product in a processor for performing in-memory tracing using existing communication paths App 20060184833 - Al-Omari; Ra'ed Mohammad ; et al.	2006-08-17
Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing App 20060184836 - Al-Omari; Ra'ed Mohammad ; et al.	2006-08-17
Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers App 20060184834 - Al-Omari; Ra'ed Mohammad ; et al.	2006-08-17
Data processing system and method for efficient communication utilizing an Ig coherency state App 20060179247 - Fields; James Stephen JR. ; et al.	2006-08-10
Half-good mode for large L2 cache array topology with different latency domains App 20060179230 - Fields; James Stephen JR. ; et al.	2006-08-10
Cache member protection with partial make MRU allocation App 20060179234 - Bell; Robert H. JR. ; et al.	2006-08-10
L2 cache array topology for large cache with different latency domains App 20060179223 - Clark; Leo James ; et al.	2006-08-10
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states App 20060179245 - Fields; James Stephen JR. ; et al.	2006-08-10
Data processing system and method for efficient L3 cache directory management App 20060179250 - Guthrie; Guy Lynn ; et al.	2006-08-10
L2 cache controller with slice directory and unified cache structure App 20060179229 - Clark; Leo James ; et al.	2006-08-10
Data processing system and method for efficient coherency communication utilizing coherency domains App 20060179243 - Fields; James Stephen JR. ; et al.	2006-08-10
System and method of re-ordering store operations within a processor App 20060179226 - Guthrie; Guy Lynn ; et al.	2006-08-10
Data processing system and method for efficient coherency communication utilizing coherency domain indicators App 20060179246 - Fields; James Stephen JR. ; et al.	2006-08-10
Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation App 20060179235 - Bell; Robert H. JR. ; et al.	2006-08-10
Pipelining D states for MRU steerage during MRU/LRU member allocation App 20060179232 - Bell; Robert H. JR. ; et al.	2006-08-10
Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism Grant 7,069,494 - Cargnoni , et al. June 27, 2	2006-06-27
Data processing system providing hardware acceleration of input/output (I/O) communication Grant 7,047,320 - Arimilli , et al. May 16, 2	2006-05-16
Programming means for dynamic specifications of cache management preferences Grant 7,039,760 - Arimilli , et al. May 2, 2	2006-05-02
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems Grant 7,039,832 - Arimilli , et al. May 2, 2	2006-05-02
Processor, data processing system and method for synchronizing access to data in shared memory App 20060085604 - Guthrie; Guy Lynn ; et al.	2006-04-20
Processor, data processing system and method for synchronzing access to data in shared memory App 20060085605 - Guthrie; Guy Lynn ; et al.	2006-04-20
Processor, data processing system and method for synchronzing access to data in shared memory App 20060085603 - Guthrie; Guy Lynn ; et al.	2006-04-20
Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members Grant 6,996,679 - Cargnoni , et al. February 7, 2	2006-02-07
Cache allocation mechanism for saving elected unworthy member via substitute victimization and imputed worthiness of substitute victim member Grant 6,993,628 - Starke January 31, 2	2006-01-31
Dynamically managing saved processor soft states Grant 6,983,347 - Arimilli , et al. January 3, 2	2006-01-03
Processor virtualization mechanism via an enhanced restoration of hard architected states Grant 6,981,083 - Arimilli , et al. December 27, 2	2005-12-27
Acceleration of input/output (I/O) communication through improved address translation Grant 6,976,148 - Arimilli , et al. December 13, 2	2005-12-13
Circuits and methods for recovering link stack data upon branch instruction mis-speculation Grant 6,848,044 - Eisen , et al. January 25, 2	2005-01-25
Programming means for dynamic specifications of cache management preferences App 20040215888 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Cache allocation mechanism for saving elected unworthy member via substitute victimization and imputed worthiness of substitute victim member App 20040215887 - Starke, William John	2004-10-28
Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members App 20040215889 - Cargnoni, Robert Alan ; et al.	2004-10-28
Cache allocation mechanism for biasing subsequent allocations based upon cache directory state App 20040215890 - Cargnoni, Robert Alan ; et al.	2004-10-28
Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism App 20040210814 - Cargnoni, Robert Alan ; et al.	2004-10-21
Cache directory array recovery mechanism to support special ECC stuck bit matrix App 20040210799 - Cargnoni, Robert Alan ; et al.	2004-10-21
Method and apparatus for using past history to avoid flush conditions in a microprocessor Grant 6,804,770 - Logan , et al. October 12, 2	2004-10-12
High speed virtual instruction execution mechanism App 20040139304 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Data processing system providing hardware acceleration of input/outpuit (I/O) communication App 20040139246 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Acceleration of input/output (I/O) communication through improved address translation App 20040139295 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Cache coherent I/O communication App 20040139283 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Hardware-enabled instruction tracing App 20040139305 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Dynamically managing saved processor soft states App 20040111562 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states App 20040111591 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/ systems App 20040111653 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Managing processor architected state upon an interrupt App 20040111572 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Cross partition sharing of state information App 20040111552 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Interrupt handler prediction method and system App 20040111593 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Processor virtualization mechanism via an enhanced restoration of hard architected states App 20040111548 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Method system and apparatus for instruction tracing with out of order processors Grant 6,694,427 - Mericas , et al. February 17, 2	2004-02-17
Method and apparatus for allocating data usages within an embedded dynamic random access memory device Grant 6,678,814 - Arimilli , et al. January 13, 2	2004-01-13
Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache Grant 6,651,162 - Levitan , et al. November 18, 2	2003-11-18
High speed lock acquisition mechanism with time parameterized cache coherency states Grant 6,629,212 - Arimilli , et al. September 30, 2	2003-09-30
Cache coherency protocol permitting sharing of a locked data granule Grant 6,629,209 - Arimilli , et al. September 30, 2	2003-09-30
Extended cache coherency protocol with a persistent "lock acquired" state Grant 6,629,214 - Arimilli , et al. September 30, 2	2003-09-30
Extended cache coherency protocol with a modified store instruction lock release indicator Grant 6,625,701 - Arimilli , et al. September 23, 2	2003-09-23
Method and system for controlling information flow between a producer and a buffer in a high frequency digital system Grant 6,606,666 - Bell, Jr. , et al. August 12, 2	2003-08-12
Method and apparatus for accessing banked embedded dynamic random access memory devices Grant 6,606,680 - Arimilli , et al. August 12, 2	2003-08-12
Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path Grant 6,604,145 - Bell, Jr. , et al. August 5, 2	2003-08-05
Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system Grant 6,601,105 - Bell, Jr. , et al. July 29, 2	2003-07-29
Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer Grant 6,598,086 - Bell, Jr. , et al. July 22, 2	2003-07-22
Extended cache coherency protocol with a "lock released" state Grant 6,549,989 - Arimilli , et al. April 15, 2	2003-04-15
Method And Apparatus For Concurrently Communicating With Multiple Embedded Dynamic Random Access Memory Devices App 20030014606 - Arimilli, Ravi Kumar ; et al.	2003-01-16
Method and apparatus for accessing banked embedded dynamic random access momory devices App 20030005211 - Arimilli, Ravi Kumar ; et al.	2003-01-02
Method and apparatus for allocating data usages within an embedded dynamic random access memory device App 20030005215 - Arimilli, Ravi Kumar ; et al.	2003-01-02
Reducing resource collisions associated with memory units in a multi-level hierarchy memory system Grant 6,493,814 - Fields, Jr. , et al. December 10, 2	2002-12-10
Method and system for clearing dependent speculations from a request queue Grant 6,487,637 - Arimilli , et al. November 26, 2	2002-11-26
Method and apparatus for using past history to avoid flush conditions in a microprocessor App 20020138713 - Logan, Douglas Robert ; et al.	2002-09-26
Circuits and methods for recovering link stack data upon branch instruction mis-speculation App 20020129226 - Eisen, Lee Evan ; et al.	2002-09-12
Reducing resource collisions associated with memory units in a multi-level hierarchy memory system App 20020129220 - Fields, James Stephen JR. ; et al.	2002-09-12
Method and system for cancelling speculative cache prefetch requests Grant 6,438,656 - Arimilli , et al. August 20, 2	2002-08-20
Partitioned cache and management method for selectively caching data by type Grant 6,421,761 - Arimilli , et al. July 16, 2	2002-07-16
Method and system for managing speculative requests in a multi-level memory hierarchy Grant 6,418,516 - Arimilli , et al. July 9, 2	2002-07-09
Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line Grant 6,345,342 - Arimilli , et al. February 5, 2	2002-02-05
High performance multiprocessor system with modified-unsolicited cache state Grant 6,321,306 - Arimilli , et al. November 20, 2	2001-11-20
Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation Grant 6,075,937 - Scalzi , et al. June 13, 2	2000-06-13
Preprocessing of stored target routines for emulating incompatible instructions on a target processor Grant 6,009,261 - Scalzi , et al. December 28, 1	1999-12-28
Method and system for initial state determination for instruction trace reconstruction Grant 5,894,575 - Levine , et al. April 13, 1	1999-04-13
Apparatus and method for executing instructions that select a storage location for output values in response to an operation count Grant 5,889,947 - Starke March 30, 1	1999-03-30