Standaert; Theodorus Eduardus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Standaert; Theodorus Eduardus.The latest application filed is for "structure and method to improve fav rie process margin and electromigration".

Company Profile

0.30.31

Standaert; Theodorus Eduardus - Clifton Park NY
Standaert; Theodorus Eduardus - Albany NY
Standaert; Theodorus Eduardus - Hopewell Junction NY US
Standaert; Theodorus Eduardus - Pine Bush NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structure And Method To Improve Fav Rie Process Margin And Electromigration App 20210210380 - Briggs; Benjamin David ; et al.	2021-07-08
Structure and method to improve FAV RIE process margin and Electromigration Grant 10,985,056 - Briggs , et al. April 20, 2	2021-04-20
Structure and method to improve FAV RIE process margin and electromigration Grant 10,957,584 - Briggs , et al. March 23, 2	2021-03-23
Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects Grant 10,134,674 - Briggs , et al. November 20, 2	2018-11-20
Structure And Method To Improve Fav Rie Process Margin And Electromigration App 20180122691 - Briggs; Benjamin David ; et al.	2018-05-03
Structure And Method To Improve Fav Rie Process Margin And Electromigration App 20180122692 - Briggs; Benjamin David ; et al.	2018-05-03
Structure And Method To Improve Fav Rie Process Margin And Electromigration App 20180114723 - Briggs; Benjamin David ; et al.	2018-04-26
Structure and method to improve FAV RIE process margin and electromigration Grant 9,953,865 - Briggs , et al. April 24, 2	2018-04-24
Structure And Method For Improved Stabilization Of Cobalt Cap And/or Cobalt Liner In Interconnects App 20180005953 - Briggs; Benjamin D. ; et al.	2018-01-04
Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects Grant 9,780,035 - Briggs , et al. October 3, 2	2017-10-03
Method and structure to reduce the electric field in semiconductor wiring interconnects Grant 9,666,529 - Huang , et al. May 30, 2	2017-05-30
Self-aligned dielectric isolation for FinFET devices Grant 9,627,377 - Bergendahl , et al. April 18, 2	2017-04-18
FinFET with dielectric isolation by silicon-on-nothing and method of fabrication Grant 9,478,549 - Cheng , et al. October 25, 2	2016-10-25
Method and structure to reduce the electric field in semiconductor wiring interconnects Grant 9,379,057 - Huang , et al. June 28, 2	2016-06-28
Semiconductor structure with deep trench thermal conduction Grant 9,349,838 - Cheng , et al. May 24, 2	2016-05-24
Semiconductor structure with deep trench thermal conduction Grant 9,331,177 - Cheng , et al. May 3, 2	2016-05-03
Method And Structure To Reduce The Electric Field In Semiconductor Wiring Interconnects App 20160064321 - Huang; Elbert Emin ; et al.	2016-03-03
Method And Structure To Reduce The Electric Field In Semiconductor Wiring Interconnects App 20160064330 - Huang; Elbert Emin ; et al.	2016-03-03
Dummy fin formation by gas cluster ion beam Grant 9,269,629 - Cheng , et al. February 23, 2	2016-02-23
Semiconductor structure with deep trench thermal conduction Grant 9,252,242 - Standaert , et al. February 2, 2	2016-02-02
FinFET with dielectric isolation by silicon-on-nothing and method of fabrication Grant 9,219,068 - Cheng , et al. December 22, 2	2015-12-22
Finfet With Dielectric Isolation By Silicon-on-nothing And Method Of Fabrication App 20150340288 - Cheng; Kangguo ; et al.	2015-11-26
Method and structure for finFET with finely controlled device width Grant 9,082,873 - Yamashita , et al. July 14, 2	2015-07-14
FinFET with dielectric isolation by silicon-on-nothing and method of fabrication Grant 9,000,522 - Cheng , et al. April 7, 2	2015-04-07
Dummy Fin Formation By Gas Cluster Ion Beam App 20150064874 - Cheng; Kangguo ; et al.	2015-03-05
Finfet With Dielectric Isolation By Silicon-on-nothing And Method Of Fabrication App 20150064855 - Cheng; Kangguo ; et al.	2015-03-05
Self-aligned Dielectric Isolation For Finfet Devices App 20150061040 - Bergendahl; Marc Adam ; et al.	2015-03-05
Semiconductor Structure With Deep Trench Thermal Conduction App 20150054082 - Cheng; Kangguo ; et al.	2015-02-26
Dummy fin formation by gas cluster ion beam Grant 8,946,792 - Cheng , et al. February 3, 2	2015-02-03
Self-aligned dielectric isolation for FinFET devices Grant 8,941,156 - Bergendahl , et al. January 27, 2	2015-01-27
Semiconductor Structure With Deep Trench Thermal Conduction App 20140284717 - Standaert; Theodorus Eduardus ; et al.	2014-09-25
FinFET trench circuit Grant 8,835,250 - Faltermeier , et al. September 16, 2	2014-09-16
Self-aligned Dielectric Isolation For Finfet Devices App 20140191296 - Bergendahl; Marc Adam ; et al.	2014-07-10
Finfet With Dielectric Isolation By Silicon-on-nothing And Method Of Fabrication App 20140191321 - Cheng; Kangguo ; et al.	2014-07-10
Finfet Compatible Diode For Esd Protection App 20140191319 - Cheng; Kangguo ; et al.	2014-07-10
Replacement metal gate transistors using bi-layer hardmask Grant 8,748,252 - Leobandung , et al. June 10, 2	2014-06-10
Replacement Metal Gate Transistors Using Bi-layer Hardmask App 20140148003 - Leobandung; Effendi ; et al.	2014-05-29
Dummy Fin Formation By Gas Cluster Ion Beam App 20140145248 - Cheng; Kangguo ; et al.	2014-05-29
Method And Structure For Finfet With Finely Controlled Device Width App 20140077296 - Yamashita; Tenko ; et al.	2014-03-20
Finfet Trench Circuit App 20140070294 - Faltermeier; Jonathan E. ; et al.	2014-03-13
FinFET diode with increased junction area Grant 8,592,263 - Standaert , et al. November 26, 2	2013-11-26
Finfet Diode With Increased Junction Area App 20130285208 - Standaert; Theodorus Eduardus ; et al.	2013-10-31
FinFET with improved gate planarity Grant 8,569,125 - Standaert , et al. October 29, 2	2013-10-29
Method And Structure For Inline Electrical Fin Critical Dimension Measurement App 20130173214 - Yamashita; Tenko ; et al.	2013-07-04
Finfet With Improved Gate Planarity App 20130134513 - Standaert; Theodorus Eduardus ; et al.	2013-05-30
Capping of copper interconnect lines in integrated circuit devices Grant 8,298,948 - Bonilla , et al. October 30, 2	2012-10-30
CMOS devices with different metals in gate electrodes using spin on low-k material as hard mask Grant 7,943,453 - Kastenmeier , et al. May 17, 2	2011-05-17
Reliability of wide interconnects Grant 7,776,737 - Bonilla , et al. August 17, 2	2010-08-17
Reliability Of Wide Interconnects App 20100038790 - Bonilla; Griselda ; et al.	2010-02-18
Cmos Devices With Different Metals In Gate Electrodes Using Spin On Low-k Material As Hard Mask App 20090159991 - Kastenmeier; Bernd Ernst Eduard ; et al.	2009-06-25
Interconnect structure and process of making the same Grant 7,488,679 - Standaert , et al. February 10, 2	2009-02-10
Interconnect Structure And Process Of Making The Same App 20080026568 - Standaert; Theodorus Eduardus ; et al.	2008-01-31